Abstract: A multi-frequency platform for metal detection is disclosed. The transmission frequencies may be selected by the user or in an autonomous fashion. Further, the weighting of the frequencies may also be selected, either by the user or in an autonomous fashion. The ability to select transmission frequencies and weighting of the frequencies provides expanded detection capability, both in terms of the types of targets being sought and the types of ground conditions being experienced.

Abstract: A multi-frequency platform for metal detection is disclosed. The transmission frequencies may be selected by the user or in an autonomous fashion. Further, the weighting of the frequencies may also be selected, either by the user or in an autonomous fashion. The ability to select transmission frequencies and weighting of the frequencies provides expanded detection capability, both in terms of the types of targets being sought and the types of ground conditions being experienced.

Abstract: A metal detector has a motion sensor such as an accelerometer to determine direction, speed, duration and acceleration of search loop motion. The search loop motion information from the motion sensor is utilized in mode selection, signal processing, target analysis, and information display.

Abstract: This invention provides a pulse induction metal detector where a coil transmits a pulsed magnetic field to energize metal objects that are often buried or hidden in a matrix (ground) containing ferromagnetic minerals. A difficult challenge is to detect and identify the metal object while ignoring the ferromagnetic matrix. Techniques are presented for achieving this.

Abstract: Synthesizer structures and alignment methods are provided that facilitate quadrature demodulation. The structures are realized with phase-locked loops that include half-rate frequency dividers to provide loop output signals with a wide range of output frequencies and with frequency dividers that provide quadrature signals in response to the output signals. The structures include controllers that direct alignment methods which lock a VCO to a reference signal from a reference frequency divider to thereby provide the output signals.

Abstract: Variable-gain amplifiers (VGAs) are provided that realize gain accuracy (e.g., over variations in temperature and fabrication processes) while also providing this accuracy over a wide bandwidth and without the signal-to-noise degradation typically associated with signal attentuating elements. Differential signal and gain amplifiers of these VGAs include current sources which are controlled by a common error signal Serr. The gain amplifier is supplemented by feedback structure that generates the error signal Serr and controls the amplifier's transconductance to be the ratio of at least one of currents and resistors. Because such ratios can be well matched (especially in integrated circuit realizations of the variable-gain amplifiers) and because the current source of the signal amplifier is also controlled by the error signal Serr, this wide-band, low-noise open-loop amplifier's gain is accurately controlled.

Abstract: Pipelined ADC systems are provided with gain-matching structures that substantially eliminate gain errors between preceding and succeeding converter stages. These structures include reference signal-conditioning elements which mimic at least one of main signal-conditioning elements in the succeeding converter stages. The reference signal-conditioning elements control reference signals which maintain a match between the full-scale range of a digital-to-analog converter (DAC) in a succeeding stage and the “gained-up” step size of a DAC in a preceding stage. This match substantially eliminates the gain errors.

Abstract: Latch systems and methods are configured to temporarily latch trim signals in experimental combinations of set and reset states and, subsequently, to permanently latch the trim signals in a preferred combination (i.e., a combination that optimizes the performance parameters of an electronic circuit). Latch systems of the invention include a latch, a reset driver, a temporary-set driver and a permanent-set driver and are particularly suited for determining a preferred combination of set and reset states prior to permanently latching this preferred combination.

Abstract: N-bit precision digital-to-analog converters are provided that facilitate realization of precision linearities (i.e., linearities that substantially exceed N-bit linearity). They include a binary-weighted current source, current switches and bidirectional-trim digital-to-analog converters. The binary-weighted current source generates binary-weighted currents that are each coupled to the output port by a respective one of the current switches in response to a respective bit of the digital input signal. The bidirectional-trim digital-to-analog converters generate respective bidirectional trim currents with respective amplitudes and directions. Each of the bidirectional-trim digital-to-analog converters is coupled to provide its bidirectional trim current to a respective one of the current switches for a linearizing adjustment of that switch's binary-weighted current. Preferably, the bidirectional-trim currents are slaved to the binary-weighted currents.

Abstract: A bandgap reference circuit provides an output reference voltage that is generally insensitive to fluctuations in supply voltage, ambient temperature, and output load current. A current regulator establishes an output whose variations are reduced, preferably logarithmically, relative to variations in a supply voltage. A bandgap generator fed by the output current provides an output reference voltage with similarly suppressed variations. A control amplifier biases the bandgap generator to provide a high level common-mode rejection of various error sources.

Abstract: High-speed signal translators are provided to convert differential input signals (e.g., ECL signals) to single-ended output signals (e.g., CMOS signals). An exemplary translator is formed with first and second current mirrors, first and second complimentary differential pairs of transistors, a complimentary transistor output stage and first and second current-diverting transistors. The complimentary output stage initially generates the single-ended output signal in response to currents received from the complimentary differential pairs. When the output signal has been established, the current-diverting transistors respond by carrying at least portions of the currents supplied by the complimentary differential pairs. The current-diverting transistors also drive the current mirrors to divert other portions of these currents away from the complimentary output stage. Stored charges in the output stage are accordingly reduced and its response time enhanced.

Abstract: Linearized unity-gain folding amplifiers include first and second differential pairs of transistors that have offset voltages between control terminals and first current terminals. The control terminals are differentially coupled through input paths to a differential input port and the joined first current terminals receive respective first and second currents through respective first and second level-shift resistors. Thus, folded and level-shifted signals can be differentially coupled via output paths between the first and second level-shift resistors and an output port. For each of the differential pairs, at least one correction voltage is generated to substantially match the offset voltage of one of the transistors of that differential pair when a differential input voltage has one polarity and the offset voltage of another of the transistors when the differential input voltage has a different polarity.

Abstract: A clock-to-clock auto-ranging ADC operates directly on an analog signal in the IF band or higher to track its gain range on a clock-to-clock basis and produce a digital signal that maintains high resolution of the analog signal without clipping or loss of signal sensitivity. This is accomplished by sampling an analog signal of sufficiently high frequency that a peak detector can accurately determine the maximum signal level over at least one-half a signal period and then reset the signal gain going into the ADC prior to the beginning of the next sampling period. This insures that the analog signal will always be within the range of the ADC. In accordance with the well known principles of sampling theory, the sampled analog signal is aliased into the frequency region between DC and one half the sampling frequency.

Abstract: A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized.

Abstract: A serial-type A/D converter uses magnitude amplifiers("magamps") and comparators for effecting the conversion of analog signals to Gray scale code signals that are then converted to binary digital signals by a Gray scale code-to-binary portion of the serial-type A/D converter. More specifically, a serial-type A/D converter uses an n-bit converter that has n-1 magamps and n-comparators. The n-1 magamps are cascaded such that the V.sub.OL and V.sub.OH outputs of a stage are the inputs to the next stage. The output of the comparators are input to the Gray scale code-to-binary portion of the serial A/D converter. The latching of the comparators occurs outside of the magamps. This allows for the parallel latching of the n comparators. The speed of the serial-type A/D converter is determined by the bandwidth of the magamps. The serial-type A/D converter includes an offset method that significantly reduces the effects of early voltage, V.sub.A, on the output waveforms.

Abstract: A gain compensating differential reference circuit that is used to match the gain of an input differential amplifier, and track and hold circuit at the input of an analog-to-digital converter. The gain compensating differential reference circuit includes a single-to-differential converter to convert a V.sub.REF signal into a V.sub.REF+ and a V.sub.REF- signals whose difference equals the full-scale range of the differential analog input to the A/D converter, a gain matching differential amplifier to process to the differential output of the single-to-differential converter, and a gain matching track and hold circuit to process the output of the differential amplifier. The output of the gain matching track and hold circuit has the same gain and full-scale range as the analog signals processed by the input circuitry of the A/D converter along the analog path.

Abstract: An improved magnitude amplifier (magamp) is provided for a serial-type A/D converter. The magamp includes an improved differential input amplifier circuit to which offset circuitry is connected. These elements may be implemented in a single integrated circuit chip or as separate discrete circuits in hardware. The differential input amplifier circuit includes two pairs of differential input transistors, a comparator, and current switching control transistors. The comparator provides outputs that drive the current switching control transistors. The current switching control transistors are connected below the input transistors and not above the input transistors to reduce the parasitic capacitive loading at the outputs of the differential input amplifier circuit and increase the speed of the magamp. The offset circuitry provides the appropriate signals for aligning the output signals for output to the next stage magamp.

Abstract: A circuit for selecting between two states and using the same pin as an input and an output. On power-up, the pin can be connected to either a grounded resistor (to select the first state) or the power supply (to select the second state). The input signal generates a logic select signal. The logic select signal selects between first and second logic formats. If the first format is selected, the pin is used to output a reference voltage for that format. If the second format is selected, the logic select signal also provides a disable signal, that prevents the reference voltage output from appearing on the pin.

Abstract: A logic output stage that may be part of a circuit that provides the circuit user with the ability to select the type of digital electronic format for the digital signals output from the circuit. The logic output stage may include separate sections for processing signals so that they will have one of a plurality of digital electronic formats. Moreover, in cases where two or more digital electronic formats are very close, a single section may be used to process digital signals to have these formats.