Patents by Inventor Carl William Werner
Carl William Werner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11063741Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.Type: GrantFiled: October 21, 2019Date of Patent: July 13, 2021Assignee: RAMBUS INC.Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Publication number: 20200162233Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.Type: ApplicationFiled: October 21, 2019Publication date: May 21, 2020Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Patent number: 10454667Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.Type: GrantFiled: March 6, 2018Date of Patent: October 22, 2019Assignee: RAMBUS INC.Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Publication number: 20180262323Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.Type: ApplicationFiled: March 6, 2018Publication date: September 13, 2018Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Patent number: 9912469Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: GrantFiled: December 5, 2016Date of Patent: March 6, 2018Assignee: RAMBUS INC.Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Publication number: 20170214515Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: ApplicationFiled: December 5, 2016Publication date: July 27, 2017Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Patent number: 9515814Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: GrantFiled: August 6, 2015Date of Patent: December 6, 2016Assignee: RAMBUS INC.Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Publication number: 20160043861Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: ApplicationFiled: August 6, 2015Publication date: February 11, 2016Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Patent number: 9106399Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: GrantFiled: July 1, 2014Date of Patent: August 11, 2015Assignee: RAMBUS INC.Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Patent number: 8995598Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.Type: GrantFiled: December 6, 2011Date of Patent: March 31, 2015Assignee: Rambus Inc.Inventor: Carl William Werner
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Publication number: 20150030113Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: ApplicationFiled: July 1, 2014Publication date: January 29, 2015Inventors: Hae-Chang Lee, Jared L. Zerbe, Carl William Werner
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Patent number: 8774337Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: GrantFiled: December 10, 2012Date of Patent: July 8, 2014Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Publication number: 20130195234Abstract: A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: ApplicationFiled: December 10, 2012Publication date: August 1, 2013Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Patent number: 8498344Abstract: A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.Type: GrantFiled: June 18, 2009Date of Patent: July 30, 2013Assignee: Rambus Inc.Inventors: John M. Wilson, Aliazam Abbasfar, John Eble, III, Lei Luo, Jade M. Kizer, Carl William Werner, Wayne Dettloff
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Patent number: 8331512Abstract: A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: GrantFiled: April 4, 2007Date of Patent: December 11, 2012Assignee: Rambus Inc.Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Publication number: 20120200325Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.Type: ApplicationFiled: December 6, 2011Publication date: August 9, 2012Inventor: Carl William Werner
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Patent number: 8085893Abstract: A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.Type: GrantFiled: September 13, 2005Date of Patent: December 27, 2011Assignee: Rambus, Inc.Inventor: Carl William Werner
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Publication number: 20110127990Abstract: A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.Type: ApplicationFiled: June 18, 2009Publication date: June 2, 2011Applicant: RAMBUS INC.Inventors: John M. Wilson, Aliazam Abbasfar, John Eble, III, Lei Luo, Jade M. Kizer, Carl William Werner, Wayne Dettloff
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Publication number: 20090310667Abstract: A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.Type: ApplicationFiled: April 4, 2007Publication date: December 17, 2009Inventors: Hae-Chang Lee, Jared LeVan Zerbe, Carl William Werner
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Patent number: 7308044Abstract: A technique for receiving differential multi-PAM signals is disclosed. In one particular exemplary embodiment, the technique may be realized as a differential multi-PAM extractor circuit. In this particular exemplary embodiment, the differential multi-PAM extractor circuit comprises an upper LSB sampler circuit configured to receive a differential multi-PAM input signal and a first differential reference signal, and to generate a first differential sampled output signal. The differential multi-PAM extractor circuit also comprises a lower LSB sampler circuit configured to receive the differential multi-PAM input signal and a second differential reference signal, and to generate a second differential sampled output signal.Type: GrantFiled: September 30, 2003Date of Patent: December 11, 2007Assignee: Rambus IncInventors: Jared LeVan Zerbe, Grace Tsang, Mark Horowitz, Bruno Werner Garlepp, Carl William Werner