Patents by Inventor Carlo Dario FANARA
Carlo Dario FANARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11593111Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided.Type: GrantFiled: January 27, 2020Date of Patent: February 28, 2023Assignee: Arm LimitedInventors: Frederic Jean Denis Arsanto, Carlo Dario Fanara, Luca Scalabrino, Jean Sébastien Leroy
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Patent number: 11449642Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.Type: GrantFiled: September 4, 2020Date of Patent: September 20, 2022Assignee: Arm LimitedInventors: Carlo Dario Fanara, Frederic Jean Denis Arsanto, Luca Scalabrino
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Publication number: 20220075901Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.Type: ApplicationFiled: September 4, 2020Publication date: March 10, 2022Applicant: Arm LimitedInventors: Carlo Dario Fanara, Frederic Jean Denis Arsanto, Luca Scalabrino
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Patent number: 11263014Abstract: Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided.Type: GrantFiled: August 5, 2019Date of Patent: March 1, 2022Assignee: Arm LimitedInventors: Frederic Claude Marie Piry, Thomas Christoper Grocutt, Simon John Craske, Carlo Dario Fanara, Jean Sébastien Leroy
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Publication number: 20210232396Abstract: An apparatus and method are provided for inhibiting instruction manipulation. The apparatus has execution circuitry for performing data processing operations in response to a sequence of instructions from an instruction set, and decoder circuitry for decoding each instruction in the sequence in order to generate control signals for the execution circuitry. Each instruction comprises a plurality of instruction bits, and the decoder circuitry is arranged to perform a decode operation on each instruction to determine from the value of each instruction bit, and knowledge of the instruction set, the control signals to be issued to the execution circuitry in response to that instruction. An input path to the decoder circuitry comprises a set of wires over which the instruction bits of each instruction are provided.Type: ApplicationFiled: January 27, 2020Publication date: July 29, 2021Inventors: Frederic Jean Denis ARSANTO, Carlo Dario FANARA, Luca SCALABRINO, Jean Sébastien LEROY
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Publication number: 20210042124Abstract: Data processing apparatuses, methods of data processing, and non-transitory computer-readable media on which computer-readable code is stored defining logical configurations of processing devices are disclosed. In an apparatus, fetch circuitry retrieves a sequence of instructions and execution circuitry performs data processing operations with respect to data values in a set of registers. An auxiliary execution circuitry interface and a coprocessor interface to provide a connection to a coprocessor outside the apparatus are provided.Type: ApplicationFiled: August 5, 2019Publication date: February 11, 2021Inventors: Frederic Claude Marie PIRY, Thomas Christoper GROCUTT, Simon John CRASKE, Carlo Dario FANARA, Jean Sébastien LEROY
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Patent number: 10902113Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.Type: GrantFiled: October 25, 2017Date of Patent: January 26, 2021Assignee: ARM LimitedInventors: Guillaume Schon, Frederic Jean Denis Arsanto, Carlo Dario Fanara, Jocelyn François Orion Jaubert
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Patent number: 10572262Abstract: An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.Type: GrantFiled: July 17, 2017Date of Patent: February 25, 2020Assignee: ARM LimitedInventors: Jocelyn Francois Orion Jaubert, Frederic Jean Denis Arsanto, Guillaume Schon, Carlo Dario Fanara
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Patent number: 10540299Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.Type: GrantFiled: June 30, 2017Date of Patent: January 21, 2020Assignee: ARM LimitedInventors: Carlo Dario Fanara, Frederic Jean Denis Arsanto, Guillaume Schon, Jocelyn Francois Orion Jaubert
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Patent number: 10445500Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.Type: GrantFiled: June 28, 2017Date of Patent: October 15, 2019Assignee: ARM LimitedInventors: Guillaume Schon, Frederic Jean Denis Arsanto, Jocelyn François Orion Jaubert, Carlo Dario Fanara
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Publication number: 20190121967Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Guillaume SCHON, Frederic Jean Denis ARSANTO, Carlo Dario FANARA, Jocelyn François Orion JAUBERT
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Publication number: 20190018686Abstract: An apparatus comprising: a set of registers; and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.Type: ApplicationFiled: July 17, 2017Publication date: January 17, 2019Inventors: Jocelyn Francois Orion JAUBERT, Frederic Jean Denis ARSANTO, Guillaume SCHON, Carlo Dario FANARA
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Publication number: 20190004977Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Carlo Dario FANARA, Frederic Jean Denis ARSANTO, Guillaume SCHON, Jocelyn Francois Orion JAUBERT
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Publication number: 20190005240Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.Type: ApplicationFiled: June 28, 2017Publication date: January 3, 2019Inventors: Guillaume SCHON, Frederic Jean Denis ARSANTO, Jocelyn François Orion JAUBERT, Carlo Dario FANARA
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Patent number: 9646160Abstract: An apparatus and method are provided for enhancing resilience to attacks on reset of the apparatus. The apparatus comprises at least one storage element, and update circuitry that is configured to receive obscuring data, and which is responsive to a reset event to store in each of the at least one storage element a data value that is dependent on the current value of the obscuring data. For each such storage element, this ensures that the data value stored in that storage element is unpredictable following each reset event, thereby preventing the reproducibility of certain steps that would typically be taken by an attacker during an attack on the apparatus.Type: GrantFiled: September 8, 2014Date of Patent: May 9, 2017Assignee: ARM LimitedInventors: Yohann Fred Arifidy Rabefarihy, Carlo Dario Fanara, Stephane Zonza, Jean-Baptiste Brelot
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Publication number: 20170061137Abstract: An apparatus and method are provided for enhancing resilience to attacks on reset of the apparatus. The apparatus comprises at least one storage element, and update circuitry that is configured to receive obscuring data, and which is responsive to a reset event to store in each of the at least one storage element a data value that is dependent on the current value of the obscuring data. For each such storage element, this ensures that the data value stored in that storage element is unpredictable following each reset event, thereby preventing the reproducibility of certain steps that would typically be taken by an attacker during an attack on the apparatus.Type: ApplicationFiled: September 8, 2014Publication date: March 2, 2017Inventors: Yohann Fred Arifidy RABEFARIHY, Carlo Dario FANARA, Stephane ZONZA, Jean-Baptiste BRELOT