Patents by Inventor Carlo Gamboa

Carlo Gamboa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8436460
    Abstract: A leadframe and semiconductor device package with multiple semiconductor device die paddles for accepting multiple semiconductor devices is disclosed, wherein the leadframe increases semiconductor device density and reduces cost by integrating the multiple dies into a semiconductor device package with a relatively small footprint. The leadframe may include at least one full-metal die paddle and at least one reduced-metal die paddle, which may form a unified or hybrid die paddle. The leadframe may enable electrical coupling of multiple semiconductor devices to a common leadfinger and/or die paddle, where internal leadfingers coupled to the common leadfingers and/or die paddles may receive the electrical coupling means from the semiconductor device. Surfaces of one or more die paddles of the leadframe may be exposed to the outside of the semiconductor device package to enable electrical testing of and/or provide heat dissipation from one or more of the semiconductor devices attached to the leadframe.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 7, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Carlo Gamboa, Bo Chang
  • Patent number: 8283772
    Abstract: A semiconductor device package, a method of fabricating a semiconductor device package and a method of testing an integrated circuit utilizing a semiconductor device package are disclosed. Embodiments create a flip-flop semiconductor device package by coupling a semiconductor device, with a wire-bonded arrangement of conductive pads, in a face-up orientation beneath multiple bent leadfingers. The flip-flop package offers improved signaling properties, durability, reliability, and package density at reduced cost given that the conductive pads of the device couple directly to the bent leadfingers, without requiring the manufacture of a new device or the rerouting of signal paths. Additionally, the flip-flop configuration provides convenient means for exposing surfaces of the device (e.g., to increase heat transfer therefrom, thermal performance of the device, etc.) and/or surfaces of the leadfingers (e.g., to provide test points, wire bondouts, etc.).
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: October 9, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventor: Carlo Gamboa
  • Patent number: 8106489
    Abstract: A package and packaging method are provided that enable packaging of larger dies and/or smaller packages. Generally, the method includes steps of: (i) reducing a thickness of a portion of a top surface of leads of a leadframe extending into a package being formed; (ii) mounting a die to a paddle of the leadframe, the die extending past an edge of the paddle into a space created by reducing the thickness of the leads; and (iii) encapsulating the die and leadframe, including the reduced portion of the leads, in a molding compound. In one embodiment, the leads are reduced by half-etching the portion of the top surface. Preferably, the method further includes wire bonding pads on the die to etched portions of the leads to electrically couple the die to the leads. Alternatively, wire bonding is between the pads and non-etched portions of the leads. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: January 31, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Carlo Gamboa, Salvador Padre
  • Patent number: 8017445
    Abstract: A method and packaging for semiconductor devices and integrated circuits is disclosed that eliminates warpage stress on packages caused by coefficient of thermal expansion (CTE) mismatch between the device, lead frame or die paddle and a molding compound. Generally, the method includes steps of: (i) mounting the die on which the device is fabricated to a die paddle of a leadframe; and (ii) encapsulating the die on the die paddle and at least a portion of the leadframe in a molding compound, wherein a difference between a first volume of molding compound above a plane of the leadframe and a second volume of molding compound below the plane of the leadframe is sufficiently reduced to substantially eliminate warpage of the finished package due to mismatch of CTEs of the device, lead frame and packaging compound. The die paddle may be etched or reduced to facilitate molding compound flowing under the plane of the leadframe. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: September 13, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Bo Chang, Carlo Gamboa
  • Publication number: 20070206650
    Abstract: A semiconductor device comprising an integrated circuit die and an electronic component mounted to the integrated circuit dies wherein the electronic component comprises a light emitting active area arranged to emit light.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 6, 2007
    Inventors: Karthik Ranganathan, Gary Gibbs, Carlo Gamboa