Patents by Inventor Carlos Basto
Carlos Basto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210338710Abstract: Compositions comprising silica particles having a mean size by standard particle sizing of between 0.5 nm and 20 nm are described for used in activating lymphocytes in culture or in whole blood.Type: ApplicationFiled: April 19, 2021Publication date: November 4, 2021Applicant: United Kingdom Research and InnovationInventors: Jonathan Joseph Powell, Nuno Jorge Rodrigues Faria, Rachel Elaine Hewitt, Bradley Michael Vis, Carlos Bastos
-
Patent number: 11007217Abstract: Compositions comprising silica particles having a mean size by standard particle sizing of between 0.5 nm and 20 nm are described for used in activating lymphocytes in culture or in whole blood.Type: GrantFiled: August 9, 2017Date of Patent: May 18, 2021Assignee: United Kingdom Research and InnovationInventors: Jonathan Joseph Powell, Nuno Jorge Rodrigues Faria, Rachel Elaine Hewitt, Bradley Michael Vis, Carlos Bastos
-
Patent number: 10678710Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.Type: GrantFiled: June 19, 2017Date of Patent: June 9, 2020Assignee: Synopsys, Inc.Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
-
Publication number: 20190192555Abstract: Compositions comprising silica particles having a mean size by standard particle sizing of between 0.5 nm and 20 nm are described for used in activating lymphocytes in culture or in whole blood.Type: ApplicationFiled: August 9, 2017Publication date: June 27, 2019Inventors: Jonathan Joseph Powell, Nuno Jorge Rodrigues Faria, Rachel Elaine Hewitt, Bradley Michael Vis, Carlos Bastos
-
Publication number: 20170329723Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.Type: ApplicationFiled: June 19, 2017Publication date: November 16, 2017Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
-
Patent number: 9715463Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.Type: GrantFiled: October 31, 2016Date of Patent: July 25, 2017Assignee: Synopsys, Inc.Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
-
Publication number: 20170046282Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.Type: ApplicationFiled: October 31, 2016Publication date: February 16, 2017Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
-
Patent number: 9514064Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.Type: GrantFiled: August 14, 2013Date of Patent: December 6, 2016Assignee: Synopsys, Inc.Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
-
Publication number: 20150220458Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.Type: ApplicationFiled: August 14, 2013Publication date: August 6, 2015Applicant: Synopsys, Inc.Inventors: Pranab Bhooma, Carlos Basto, Kulbhushan Kalra
-
Publication number: 20150100733Abstract: A computer system and method is disclosed for efficient cache memory organization. One embodiment of the disclosed system include dividing the tag memory into physically separated memory arrays with the entries of each array referencing cache lines in such a way that no two cache lines, which are consecutively aligned in data cache memory, reside in the same array. In another embodiment, the entries of the two memory arrays reference consecutively aligned cache lines in an alternating manner.Type: ApplicationFiled: October 2, 2014Publication date: April 9, 2015Inventors: Carlos Basto, Karthik Thucanakkenpalayam Sundararajan
-
Patent number: 8418092Abstract: A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source-synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).Type: GrantFiled: November 27, 2008Date of Patent: April 9, 2013Assignee: NXP B.V.Inventors: Carlos Basto, Jan-Willem Van De Waerdt
-
Patent number: 7975093Abstract: A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.Type: GrantFiled: October 18, 2006Date of Patent: July 5, 2011Assignee: NXP B.V.Inventors: Jan-Willem Van De Waerdt, Carlos Basto
-
Publication number: 20100271084Abstract: A method of producing an integrated circuit (700) using a system-on-chip (SoC) architecture includes providing a first circuit (710) in a first island of synchronicity (IoS); and providing a source-synchronous data link (755/757, 765/767) between the first circuit (710) in the first IoS and a hard core (720) in a second IoS for communicating n-bit data elements between the first circuit (710) and the hard core (720). The source-synchronous data link (755/757, 765/767) includes a set of n data lines (755, 765) for transporting the n-bit data elements between the first circuit (710) and the hard core (720), and a source-synchronous clock line (757, 767) for transporting a source clock between the first circuit (710) and the hard core (720) for clocking the n-bit data elements. The hard core (720) does not include a bus interface adaptor for interfacing with the source-synchronous data link (755/757, 765/767).Type: ApplicationFiled: November 27, 2008Publication date: October 28, 2010Applicant: NXP B.V.Inventors: Carlos Basto, Jan-Willem Van de Waerdt
-
Publication number: 20080209129Abstract: A cache memory system and method for supporting multiple simultaneous store operations using a plurality of tag memories is provided. The cache data system further provides a plurality of multiple simultaneous cache store functions along with a single cache load function that is simultaneous with the store functions. Embodiments create a cache memory wherein the cache write buffer does not operate as a bottle neck for data store operations into a cache memory system or device.Type: ApplicationFiled: October 18, 2006Publication date: August 28, 2008Applicant: NXP B.V.Inventors: Jan-Willem Van De Waerdt, Carlos Basto