Patents by Inventor Carlos Briseno-Vidrios
Carlos Briseno-Vidrios has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11575370Abstract: A method for establishing a powered link over a transmission line includes providing a constant, predetermined current to a terminal thereby causing a power transistor coupled to the terminal to conduct in a subthreshold region of transistor operation without current flowing between a drain terminal of the power transistor and a source terminal of the power transistor. The method includes estimating a size of the power transistor using a digital time signal indicative of an amount of time the constant, predetermined current is provided before a voltage level on the terminal exceeds a predetermined voltage level. In an embodiment, the predetermined voltage level is less than a threshold voltage of the power transistor.Type: GrantFiled: May 20, 2022Date of Patent: February 7, 2023Assignee: Skyworks Solutions, Inc.Inventors: András V. Horváth, Carlos Briseno-Vidrios, Viktor Zsolczai, Soma Ur
-
Publication number: 20220278677Abstract: A method for establishing a powered link over a transmission line includes providing a constant, predetermined current to a terminal thereby causing a power transistor coupled to the terminal to conduct in a subthreshold region of transistor operation without current flowing between a drain terminal of the power transistor and a source terminal of the power transistor. The method includes estimating a size of the power transistor using a digital time signal indicative of an amount of time the constant, predetermined current is provided before a voltage level on the terminal exceeds a predetermined voltage level. In an embodiment, the predetermined voltage level is less than a threshold voltage of the power transistor.Type: ApplicationFiled: May 20, 2022Publication date: September 1, 2022Inventors: András V. Horváth, Carlos Briseno-Vidrios, Viktor Zsolczai, Soma Ur
-
Patent number: 11342910Abstract: A method for establishing a powered link over a transmission line includes enabling a current source to provide a constant, predetermined current to a terminal. The method includes sensing a voltage on the terminal to generate a sensed voltage level. The method includes comparing the sensed voltage level on the terminal to a predetermined voltage level. The method includes disabling the current source in response to the sensed voltage level equaling or exceeding the predetermined voltage level. The method may include, while the current source is enabled, a power transistor coupled to the terminal is disabled and only conducts current in a subthreshold region of transistor operation.Type: GrantFiled: September 30, 2019Date of Patent: May 24, 2022Assignee: Skyworks Solutions, Inc.Inventors: András V. Horváth, Carlos Briseno-Vidrios, Viktor Zsolczai, Soma Ur
-
Publication number: 20210099165Abstract: A method for establishing a powered link over a transmission line includes enabling a current source to provide a constant, predetermined current to a terminal. The method includes sensing a voltage on the terminal to generate a sensed voltage level. The method includes comparing the sensed voltage level on the terminal to a predetermined voltage level. The method includes disabling the current source in response to the sensed voltage level equaling or exceeding the predetermined voltage level. The method may include, while the current source is enabled, a power transistor coupled to the terminal is disabled and only conducts current in a subthreshold region of transistor operation.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventors: András V. Horváth, Carlos Briseno-Vidrios, Viktor Zsolczai, Soma Ur
-
Patent number: 10756823Abstract: A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.Type: GrantFiled: May 9, 2018Date of Patent: August 25, 2020Assignee: Silicon Laboratories Inc.Inventors: Carlos Briseno-Vidrios, Michael R. May, Patrick J. de Bakker
-
Patent number: 10699995Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.Type: GrantFiled: May 9, 2018Date of Patent: June 30, 2020Assignee: Silicon Laboratories Inc.Inventors: Michael R. May, Charles Guo Lin, Carlos Briseno-Vidrios
-
Publication number: 20190348355Abstract: An integrated circuit isolation product includes a first integrated circuit die. The first integrated circuit die includes a first terminal and a second terminal adjacent to the first terminal. The first terminal and the second terminal are configured as a differential pair of terminals configured to communicate a differential signal across an isolation barrier. The first integrated circuit die includes at least one additional terminal adjacent to the differential pair of terminals. The at least one additional terminal is disposed symmetrically with respect to the differential pair of terminals. The first terminal may have a first parasitic capacitance and the second terminal may have a second parasitic capacitance. The first parasitic capacitance may be substantially the same as the second parasitic capacitance. The at least one additional terminal may be disposed symmetrically with respect to a line of symmetry for the differential pair of terminals.Type: ApplicationFiled: May 9, 2018Publication date: November 14, 2019Inventors: Michael R. May, Charles Guo Lin, Carlos Briseno-Vidrios
-
Publication number: 20190349095Abstract: A first die is communicatively coupled to a first isolation communication channel and a second isolation communication channel and configured to send a first heartbeat signal over the first isolation communication channel. A second die is coupled to receive the first heartbeat signal from the first die over the first isolation communication channel and to supply a second heartbeat signal to the second isolation communication channel. The first die enters a first die low power mode responsive to detecting an absence of the second heartbeat signal and the second die enters a second die low power mode responsive to detecting an absence of the first heartbeat signal. The first and second die use low power oscillators in the low power mode to supply the heartbeat signals.Type: ApplicationFiled: May 9, 2018Publication date: November 14, 2019Inventors: Carlos Briseno-Vidrios, Michael R. May, Patrick J. de Bakker
-
Patent number: 9190957Abstract: In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands.Type: GrantFiled: June 18, 2013Date of Patent: November 17, 2015Assignee: Silicon Laboratories Inc.Inventors: Mark May, Carlos Briseno-Vidrios, Junsong Li
-
Publication number: 20140370832Abstract: In an embodiment, an apparatus includes a first signal path to receive and process a radio frequency (RF) signal of a first band and which has a first programmable digitizer to convert the RF signal of the first band into a digitized signal without downconversion. In addition, the apparatus further includes a second signal path to receive and process an RF signal of a second band, where at least portions of one or more of the paths may be shared during operation in the different bands.Type: ApplicationFiled: June 18, 2013Publication date: December 18, 2014Applicant: Silicon Laboratories Inc.Inventors: Mark May, Carlos Briseno-Vidrios, Junsong Li