Patents by Inventor Carlos García Quinones

Carlos García Quinones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Branch pruning in architectures with speculation support
    Patent number: 8813057
    Abstract: According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.
    Type: Grant
    Filed: March 31, 2007
    Date of Patent: August 19, 2014
    Assignee: Intel Corporation
    Inventors: Carlos García Quiñones, Jesus Sanchez, Carlos Madriles, Pedro Marcuello, Antonio Gonzalez
  • Enabling speculative state information in a cache coherency protocol
    Patent number: 8185700
    Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: May 22, 2012
    Assignee: Intel Corporation
    Inventors: Carlos Madriles Gimeno, Carlos García Quinones, Pedro Marcuello, Jesús Sánchez, Fernando Latorre, Antonio González
  • Enabling Speculative State Information in a Cache Coherency Protocol
    Publication number: 20090083488
    Abstract: In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
    Type: Application
    Filed: May 30, 2006
    Publication date: March 26, 2009
    Inventors: Carlos Madriles Gimeno, Carlos Garcia Quinones, Pedro Marcuello, Jesus Sanchez, Fernando Latorre, Antonio Gonzalez
  • BRANCH PRUNING IN ARCHITECTURES WITH SPECULATION SUPPORT
    Publication number: 20080244223
    Abstract: According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The portion of code is optimized in the sense that the number of instructions executed will be smaller. However, since the applied optimization is speculative, the optimized version can be incorrect and some mechanism to recover from that situation is required. Thus, the quality of the produced code will be measured by taking into account both the final length of the code as well as the frequency of misspeculation.
    Type: Application
    Filed: March 31, 2007
    Publication date: October 2, 2008
    Inventors: Carlos Garcia Quinones, Jesus Sanchez, Carlos Madriles, Pedro Marcuello, Antonio Gonzalez