Patents by Inventor Carmelo Cascone

Carmelo Cascone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10708179
    Abstract: The apparatus (SW) has a plurality of input/output ports (P1, P2, P3, P4, P5) for receiving and transmitting data packets, and comprises a data packets handling circuitry (DPL) arranged to forward data packets between the input/output ports (P1, P2, P3, P4, P5) and an internal apparatus controller (CPL) arranged to control the data packet handling circuitry (DPL); the apparatus controller (CPL) is arranged to store (MEM) at least one state transition table (TT) to be used for controlling the forwarding of data packets by the data packets handling circuitry (DPL); the apparatus controller (CPL) is arranged to use the state transition table (TT) for implementing at least one finite state machine (FSM); the apparatus controller (CPL) is arranged to use the state transition table (TT) for handling separately distinct incoming data packets flows through corresponding distinct instances of finite state machine; the state transition table (TT) corresponds to the combination of a state table (ST), a condition table (
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 7, 2020
    Assignee: CONSORZIO NAZIONALE INTERUNIVERSITARIO PER LE TELECOMUNICAZIONI (CNIT)
    Inventors: Giuseppe Bianchi, Salvatore Pontarelli, Marco Bonola, Carmelo Cascone, Davide Sanvito, Antonio Capone
  • Publication number: 20190158388
    Abstract: The apparatus (SW) has a plurality of input/output ports (P1, P2, P3, P4, P5) for receiving and transmitting data packets, and comprises a data packets handling circuitry (DPL) arranged to forward data packets between the input/output ports (P1, P2, P3, P4, P5) and an internal apparatus controller (CPL) arranged to control the data packet handling circuitry (DPL); the apparatus controller (CPL) is arranged to store (MEM) at least one state transition table (TT) to be used for controlling the forwarding of data packets by the data packets handling circuitry (DPL); the apparatus controller (CPL) is arranged to use the state transition table (TT) for implementing at least one finite state machine (FSM); the apparatus controller (CPL) is arranged to use the state transition table (TT) for handling separately distinct incoming data packets flows through corresponding distinct instances of finite state machine; the state transition table (TT) corresponds to the combination of a state table (ST), a condition table (
    Type: Application
    Filed: March 27, 2017
    Publication date: May 23, 2019
    Applicant: Consorzio Nazionale Interuniversitario Per le Telecpmunicazioni (CNIT)
    Inventors: Giuseppe BIANCHI, Salvatore PONTARELLI, Marco BONOLA, Carmelo CASCONE, Davide SANVITO, Antonio CAPONE
  • Patent number: 10110489
    Abstract: The apparatus (SW) has a plurality of input/output ports (P1, P2, P3, P4, P5) for receiving and transmitting data packets, and comprises a data packets handling circuitry (DPL) arranged to forward data packets between the input/output ports (P1, P2, P3, P4, P5) and an internal apparatus controller (CPL) arranged to control the data packet handling circuitry (DPL); the apparatus (SW) has a control port (PC) for communication between the internal apparatus controller (CPL) and an external network controller (NWC); the apparatus controller (CPL) is arranged to store (MEM) at least one state transition table (TT) to be used for controlling the forwarding of data packets by the data packets handling circuitry (DPL); the apparatus controller (DPL) is arranged to use said at least one state transition table (TT) for implementing at least one finite state machine (FSM); the apparatus controller (DPL) is arranged to use said at least one state transition table (TT) for handling separately distinct incoming data packet
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 23, 2018
    Inventors: Giuseppe Bianchi, Antonio Capone, Marco Bonola, Carmelo Cascone
  • Publication number: 20170317930
    Abstract: The apparatus (SW) has a plurality of input/output ports (P1, P2, P3, P4, P5) for receiving and transmitting data packets, and comprises a data packets handling circuitry (DPL) arranged to forward data packets between the input/output ports (P1, P2, P3, P4, P5) and an internal apparatus controller (CPL) arranged to control the data packet handling circuitry (DPL); the apparatus (SW) has a control port (PC) for communication between the internal apparatus controller (CPL) and an external network controller (NWC); the apparatus controller (CPL) is arranged to store (MEM) at least one state transition table (TT) to be used for controlling the forwarding of data packets by the data packets handling circuitry (DPL); the apparatus controller (DPL) is arranged to use said at least one state transition table (TT) for implementing at least one finite state machine (FSM); the apparatus controller (DPL) is arranged to use said at least one state transition table (TT) for handling separately distinct incoming data packet
    Type: Application
    Filed: March 10, 2015
    Publication date: November 2, 2017
    Inventors: Giuseppe Bianchi, Antonio Capone, Marco Bonola, Carmelo Cascone