Patents by Inventor Carol Pincu
Carol Pincu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10622317Abstract: Aspects of the disclosure provide an integrated circuit (IC) formed on a die. The IC includes first one or more electronic circuits and a seal ring structure. The first one or more electronic circuits are disposed on a first semiconductor substrate. The first semiconductor substrate is diced from a semiconductor wafer. The seal ring structure is configured to surround the first one or more electronic circuits. The seal ring structure is formed by patterning one or more layers of metal compounds on the semiconductor wafer using two or more circuit formation process steps. The seal ring structure includes a remaining portion of a complete seal ring structure after a dicing process step that cuts the complete seal ring structure. The complete seal ring structure has been formed on the semiconductor wafer to surround the first one or more electronic circuits and at least second one or more electronic circuits on a second semiconductor substrate that is diced from the semiconductor wafer.Type: GrantFiled: March 8, 2019Date of Patent: April 14, 2020Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Abed Tatour, Carol Pincu
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Publication number: 20190206809Abstract: Aspects of the disclosure provide an integrated circuit (IC) formed on a die. The IC includes first one or more electronic circuits and a seal ring structure. The first one or more electronic circuits are disposed on a first semiconductor substrate. The first semiconductor substrate is diced from a semiconductor wafer. The seal ring structure is configured to surround the first one or more electronic circuits. The seal ring structure is formed by patterning one or more layers of metal compounds on the semiconductor wafer using two or more circuit formation process steps. The seal ring structure includes a remaining portion of a complete seal ring structure after a dicing process step that cuts the complete seal ring structure. The complete seal ring structure has been formed on the semiconductor wafer to surround the first one or more electronic circuits and at least second one or more electronic circuits on a second semiconductor substrate that is diced from the semiconductor wafer.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Applicant: Marvell Israel (M.I.S.L) Ltd.Inventors: Abed Tatour, Carol Pincu
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Patent number: 10229889Abstract: Aspects of the disclosure provide an integrated circuit (IC) formed on a die. The IC includes first one or more electronic circuits and a seal ring structure. The first one or more electronic circuits are disposed on a first semiconductor substrate. The first semiconductor substrate is diced from a semiconductor wafer. The seal ring structure is configured to surround the first one or, more electronic circuits. The seal ring structure is formed by patterning one or more layers of metal compounds on the semiconductor wafer using two or more circuit formation process steps. The seal ring structure includes a remaining portion of a complete seal ring structure after a dicing process step that cuts the complete seal ring structure. The complete seal ring structure has been formed on the semiconductor wafer to surround the first one or more electronic circuits and at least second one or more electronic circuits on a second semiconductor substrate that is diced from the semiconductor wafer.Type: GrantFiled: November 2, 2017Date of Patent: March 12, 2019Assignee: Marvell Israel (M.I.S.I.) Ltd.Inventors: Abed Tatour, Carol Pincu
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Patent number: 10204895Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is not connected to any power rail.Type: GrantFiled: February 28, 2017Date of Patent: February 12, 2019Assignee: Marvell World Trade Ltd.Inventors: Carol Pincu, Rami Rozenzvaig
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Publication number: 20170170162Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is not connected to any power rail.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Applicant: Marvell World Trade Ltd.Inventors: Carol PINCU, Rami ROZENZVAIG
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Patent number: 9601477Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component and a second power rail configured to carry the first supply voltage. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is electrically disconnected from the second power rail.Type: GrantFiled: December 18, 2015Date of Patent: March 21, 2017Assignee: Marvell World Trade Ltd.Inventors: Carol Pincu, Rami Rozenzvaig
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Patent number: 9455193Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.Type: GrantFiled: March 23, 2015Date of Patent: September 27, 2016Assignee: MARVELL ISRAEL (M.I.S.L) LTD.Inventors: Carol Pincu, Ido Bourstein
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Publication number: 20160181235Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component and a second power rail configured to carry the first supply voltage. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is electrically disconnected from the second power rail.Type: ApplicationFiled: December 18, 2015Publication date: June 23, 2016Applicant: Marvell World Trade Ltd.Inventors: Carol PINCU, Rami ROZENZVAIG
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Publication number: 20150194414Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.Type: ApplicationFiled: March 23, 2015Publication date: July 9, 2015Inventors: Carol Pincu, Ido Bourstein
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Patent number: 9006908Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.Type: GrantFiled: July 31, 2013Date of Patent: April 14, 2015Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Carol Pincu, Ido Bourstein
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Publication number: 20140035093Abstract: Systems and methods are provided for an interposer for coupling two or more integrated circuit dies to a circuit package. A first integrated circuit portion is disposed on a first location of a single semiconductor substrate. A second integrated circuit portion is disposed on a second location of the single semiconductor substrate, where the second integrated circuit portion is electrically isolated from the first integrated circuit portion along a first axis. The first and second integrated circuit portions are configured to provide an electrical coupling to two or more corresponding top die integrated circuits across a second axis that is perpendicular to the first axis.Type: ApplicationFiled: July 31, 2013Publication date: February 6, 2014Applicant: Marvell International Ltd.Inventors: Carol Pincu, Ido Bourstein