Abstract: A growth substrate adapted for making by epitaxy an array of InGaN based diodes, including mesas M(i), made of GaN based crystalline materials, each including N doped layers, with N?2, separated in pairs by an insulation intermediate layer made of a non-porous material, and each having a free upper face adapted for making a diode of the array by epitaxy; the mesas being configured according to at least three different categories including: a so-called M(N) mesas category where the N doped layers are porous; a so-called M(0) mesas category where none of the doped layers (13, 15) is porous; and a so-called M(n) mesas category where n doped layers are porous, with 1?n<N.

Abstract: A method for obtaining at least one nitride layer based upon a III-N material includes the successive steps of providing a stack having a support substrate and a plurality of pads, each pad including at least one basal section and one germination section carried by the basal section; modifying the basal section so as to form a modified basal section having a lower rigidity that the basal section before modification; and epitaxially growing a crystallite from the top of at least some of the pads of an assembly and continuing the epitaxial growth so as to form the nitride layer on pads on the assembly.

Abstract: A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically conductive doped GaN layer locally covered with InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) connecting the electrically conductive doped GaN layer and a counter-electrode (500) to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second electrode to porosify the doped InGaN layer, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: A method for manufacturing a substrate comprising the following steps of: providing a stack comprising an initial substrate, a GaN layer, a doped InGaN layer and an unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to an anodising support, so as to form a second stack, dipping the second stack and the counter-electrode into an electrolyte solution, and applying a voltage or current between the doped InGaN layer and a counter electrode, to porosify the doped InGaN layer, and relaxing the unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to a support of interest, forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically conductive doped GaN layer locally covered with InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) connecting the electrically conductive doped GaN layer and a counter-electrode (500) to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second electrode to porosify the doped InGaN layer, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: A method for manufacturing a substrate comprising the following steps of: providing a stack comprising an initial substrate, a GaN layer, a doped InGaN layer and an unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to an anodising support, so as to form a second stack, dipping the second stack and the counter-electrode into an electrolyte solution, and applying a voltage or current between the doped InGaN layer and a counter electrode, to porosify the doped InGaN layer, and relaxing the unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to a support of interest, forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: A method for manufacturing a native emission matrix, comprising the following steps: a) providing a base structure comprising a substrate, a layer of GaN, a layer of doped In(x)GaN and an epitaxial regrowth layer of nid In(x)GaN, b) structuring first and second mesas in the base structure, the first mesa comprising a part of the layer of GaN, the layer of doped In(x)GaN and the epitaxial regrowth layer of not-intentionally doped In(x)GaN, the second mesa comprising a part of the layer of doped In(x)GaN and the epitaxial regrowth layer of not-intentionally doped In(x)GaN, c) electrochemically porosifying the second mesa, d) producing stacks on the mesas to form LED structures emitting at various wavelengths.

Abstract: A method for manufacturing a relaxed epitaxial InGaN layer from a GaN/InGaN substrate comprising the following steps: a) providing a first stack comprising a GaN or InGaN layer to be porosified and a barrier layer, b) transferring the GaN or InGaN layer to be porosified and the barrier layer to a porosification support, in such a way as to form a second stack, c) forming a mask on the GaN or InGaN layer to be porosified, d) porosifying the GaN or InGaN layer through the mask, e) transferring the GaN or InGaN porosified layer and the barrier layer to a support of interest, f) forming an InGaN layer by epitaxy on the barrier layer, whereby a relaxed epitaxial InGaN layer is obtained.

Abstract: A process comprising the following steps of: a) providing a device comprising: a GaN/InGaN structure comprising an electrically conductive doped GaN layer locally covered with InGaN mesas comprising a doped InGaN layer and an undoped or weakly doped InGaN layer, an electrically insulating layer covering the electrically conductive doped GaN layer between the mesas, b) connecting the electrically conductive doped GaN layer and a counter-electrode (500) to a voltage or current generator, c) dipping the device and the counter-electrode into an electrolyte solution, d) applying a voltage or current between the electrically conductive doped GaN layer and the second electrode to porosify the doped InGaN layer, e) forming an InGaN layer by epitaxy on the InGaN mesas, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: A method for manufacturing a substrate comprising the following steps of: providing a stack comprising an initial substrate, a GaN layer, a doped InGaN layer and an unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to an anodising support, so as to form a second stack, dipping the second stack and the counter-electrode into an electrolyte solution, and applying a voltage or current between the doped InGaN layer and a counter electrode, to porosify the doped InGaN layer, and relaxing the unintentionally doped InGaN layer, transferring the doped InGaN layer and the unintentionally doped InGaN layer to a support of interest, forming an InGaN layer by epitaxy on the unintentionally doped InGaN layer, whereby a relaxed epitaxially grown InGaN layer is obtained.

Abstract: The invention relates to a process for fabricating at least one semiconductor structure (20) separated from a support substrate (11), comprising the following steps: producing a two-dimensional nucleation layer (13) starting from the support substrate (11), producing the semiconductor structure (20) by epitaxy starting from the nucleation layer, obtaining a first electrode (30) located in a lateral zone (3) which borders the semiconductor structure; placing the structure thus obtained in an aqueous electrolytic bath (50); applying a potential difference between the electrodes (30, 40) until the separation of the semiconductor structure (20) relative to the support substrate (11) is brought about.

Abstract: The invention relates to a process for fabricating an optoelectronic device (1) comprising a plurality of diodes (40), comprising the following steps: providing a readout substrate (10) containing a readout circuit (12) and having a growth face defined by a plurality of conductive segments (20) that are separate from one another and connected to the readout circuit (12); producing, on the growth face, a plurality of nucleation segments (30) made of a two-dimensional crystalline material, which segments are separate from one another, said segments resting in contact with the conductive segments (20); producing, by epitaxy from the nucleation segments (30), the plurality of diodes.

Abstract: The invention relates to a process for fabricating at least one semiconductor structure (20) separated from a support substrate (11), comprising the following steps: producing a two-dimensional nucleation layer (13) starting from the support substrate (11), producing the semiconductor structure (20) by epitaxy starting from the nucleation layer, obtaining a first electrode (30) located in a lateral zone (3) which borders the semiconductor structure; placing the structure thus obtained in an aqueous electrolytic bath (50); applying a potential difference between the electrodes (30, 40) until the separation of the semiconductor structure (20) relative to the support substrate (11) is brought about.

Abstract: A method for creating electrically conducting or semiconducting patterns on a textured surface including plural reliefs of amplitude greater than or equal to 100 nanometers, including: preparing a substrate during which at least the textured surface of the substrate is made electrically conducting; coating during which at least one layer of an imprintable material is laid on the textured surface, made electrically conducting, of the substrate; pressing a mold including valleys or protrusions to transfer the valleys or the protrusions of the mold into the imprintable material to form patterns therein; removing the mold while leaving the imprint of the patterns in the imprintable material; exposing the textured surface, made electrically conducting, of the substrate, at a bottom of the patterns; and electrically depositing an electrically conducting or semiconducting material into the patterns to form conducting or semiconducting patterns.

Abstract: A structure, method of manufacturing a structure, and methods of using a structure including a graphene sheet is disclosed. According to one aspect, the grapheme sheet is provided, on one of the faces of the structure, with a plurality of metal pins. The metal pins being separated from one another by a dielectric medium chosen from air and dielectric materials. The method including the steps of synthesizing, by vapor phase catalytic growth, the graphene sheet on a plurality of metal pins that are disposed on a membrane made from dielectric material or integrated in the membrane. The growth being catalyzed by the metal pins. According to some aspects, the membrane is removed from the structure. The structure may be used, for example, in the fields of micro- and nanoelectronics, micro- and nanoelectronic engineering, spintronics, photovoltaics, light emitting diode display, or the like.

Abstract: A support for a thin element in an electrically conducting or semi-conducting material, one face of which is intended to be put into contact with a liquid or gas medium, the support has a first part provided with a central through-passage with a longitudinal axis, said passage including at least one first and one second portion with a different diameter connected to each other through a shoulder, said shoulder being intended for supporting said thin element; a second part penetrating into the passage with the end opposite to the one intended to be exposed to the liquid solution, capable of maintaining the thin element on the shoulder; and a seal between the thin element and the shoulder.

Abstract: A method for creating electrically conducting or semiconducting patterns on a textured surface including plural reliefs of amplitude greater than or equal to 100 nanometers, including: preparing a substrate during which at least the textured surface of the substrate is made electrically conducting; coating during which at least one layer of an imprintable material is laid on the textured surface, made electrically conducting, of the substrate; pressing a mold including valleys or protrusions to transfer the valleys or the protrusions of the mold into the imprintable material to form patterns therein; removing the mold while leaving the imprint of the patterns in the imprintable material; exposing the textured surface, made electrically conducting, of the substrate, at a bottom of the patterns; and electrically depositing an electrically conducting or semiconducting material into the patterns to form conducting or semiconducting patterns.

Abstract: A semiconductor structure includes a support and at least one block provided on the support. The block includes a stack including alternating layers based on a first semiconductor material and layers based on a second semiconductor material different from the first material, the layers presenting greater dimensions than layers such that the stack has a lateral tooth profile and a plurality of spacers filling the spaces formed by the tooth profile, the spacers being made of a third material different from the first material such that each of the lateral faces of the block presents alternating lateral bands based on the first material and alternating lateral bands based on the third material. At least one of the lateral faces of the block is partially coated with a material promoting the growth of nanotubes or nanowires, the catalyst material exclusively coating the lateral bands based on the first material or exclusively coating the lateral bands based on the third material.

Abstract: A structure, method of manufacturing a structure, and methods of using a structure including a graphene sheet is disclosed. According to one aspect, the grapheme sheet is provided, on one of the faces of the structure, with a plurality of metal pins. The metal pins being separated from one another by a dielectric medium chosen from air and dielectric materials. The method including the steps of synthesizing, by vapor phase catalytic growth, the graphene sheet on a plurality of metal pins that are disposed on a membrane made from dielectric material or integrated in the membrane. The growth being catalysed by the metal pins. According to some aspects, the membrane is removed from the structure. The structure may be used, for example, in the fields of micro- and nanoelectronics, micro- and nanoelectronic engineering, spintronics, photovoltaics, light emitting diode display, or the like.

Abstract: A method for manufacturing an OLED and an electrode for an OLED, said electrode comprising a surface comprising a first dielectric nanostructuration and a second metal nanostructuration, on a substrate, wherein the following successive steps are carried out: a) a metal layer is deposited on a planar surface of a substrate; b) on the metal layer, a dielectric layer comprising said first dielectric nanostructuration which includes cavities which extend from the upper surface of the dielectric layer as far as the upper surface of the metal layer, is prepared; c) the cavities of the first dielectric nanostructuration are at least partially filled with a metal, whereby the second metal nanostructuration is obtained.