Abstract: The drive current of the switch in a switching power converter is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the switch drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the switch drive current.

Abstract: A switching power converter comprises a transformer (110), a switch (108) coupled to the transformer (110), and a switch controller (200) coupled to the switch (108) for generating a switch drive signal (207) to turn on or off the switch (108). The drive current of the switch drive signal (207) is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the drive current.

Abstract: The drive current of the switch in a switching power converter is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the switch drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the switch drive current.

Abstract: A digital phase lock loop circuit provides an output with reduced jitter. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.

Abstract: Adaptive multi-mode digital control schemes that improve the light-load efficiency (and thus the overall average efficiency) in switch-mode power converters without causing performance issues such as audible noises or excessive voltage ripples. Embodiments include a switch-mode power converter that reduces current in the power converter using a second pulse-width-modulation (PWM) mode before reaching switching frequencies that generate audible noises. As the load across the output of the power converter is reduced, the power converter transitions from a first PWM mode in high load conditions to a first pulse-frequency-modulation (PFM) mode, then to a second PWM mode, and finally to a second PFM mode. During the second PFM mode, the switching frequency is dropped to audible frequency levels. Current in the power converter, however, is reduced in the second PWM mode before transitioning to the second PFM mode.

Abstract: A switching power converter comprises a transformer (110), a switch (108) coupled to the transformer (110), and a switch controller (200) coupled to the switch (108) for generating a switch drive signal (207) to turn on or off the switch (108). The drive current of the switch drive signal (207) is adjusted dynamically according to line or load conditions within a switching cycle and/or over a plurality of switching cycles. The magnitude of the drive current can be dynamically adjusted within a switching cycle and/or over a plurality of switching cycles, in addition to the pulse widths or pulse frequencies of the drive current.

Abstract: Adaptive multi-mode digital control schemes that improve the light-load efficiency (and thus the overall average efficiency) in switch-mode power converters without causing performance issues such as audible noises or excessive voltage ripples. Embodiments include a switch-mode power converter that reduces current in the power converter using a second pulse-width-modulation (PWM) mode before reaching switching frequencies that generate audible noises. As the load across the output of the power converter is reduced, the power converter transitions from a first PWM mode in high load conditions to a first pulse-frequency-modulation (PFM) mode, then to a second PWM mode, and finally to a second PFM mode. During the second PFM mode, the switching frequency is dropped to audible frequency levels. Current in the power converter, however, is reduced in the second PWM mode before transitioning to the second PFM mode.

Abstract: A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.