Patents by Inventor Carroll S. Vance

Carroll S. Vance has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit with inter-chip link for boot-up
    Patent number: 9118374
    Abstract: An integrated circuit includes a first port for conducting a first plurality of signals, a second port for conducting a second plurality of signals, a data path coupled between the first port and the second port, a controller, and a processor having an input and an output. In a first mode, the controller causes the data path to conduct at least one signal received on the first port to the second port. In a second mode, the controller controls the processor to output signals to the second port.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: August 25, 2015
    Assignee: SILICON LABORATORIES INC.
    Inventors: Scott Thomas Haban, Wei Han, Younes Djadi, Carroll S. Vance
  • INTEGRATED CIRCUIT WITH INTER-CHIP LINK FOR BOOT-UP
    Publication number: 20150139370
    Abstract: An integrated circuit includes a first port for conducting a first plurality of signals, a second port for conducting a second plurality of signals, a data path coupled between the first port and the second port, a controller, and a processor having an input and an output. In a first mode, the controller causes the data path to conduct at least one signal received on the first port to the second port. In a second mode, the controller controls the processor to output signals to the second port.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Applicant: Silicon Laboratories Inc.
    Inventors: Scott Thomas Haban, Wei Han, Younes Djadi, Carroll S. Vance
  • Method of making three dimensional integrated circuit interconnect module
    Patent number: 5383269
    Abstract: A three dimensional integrated circuit interconnect for connecting a plurality of chips in a module with a standard footprint for pin grid array or quad flat pack mounting. Each IC is mounted on a custom interconnect slice and tested. The slices are stacked together with electrical connections from one slice layer to the next. The module may use multi-layer ceramic slices or printed circuit board materials.
    Type: Grant
    Filed: September 2, 1993
    Date of Patent: January 24, 1995
    Assignee: Microelectronics And Computer Technology Corporation
    Inventors: Claude Rathmell, Carroll S. Vance, David W. Barnes, Seyed H. Hashemi