Patents by Inventor Carsten Greiner
Carsten Greiner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10830818Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: GrantFiled: September 25, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10823782Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: GrantFiled: November 8, 2017Date of Patent: November 3, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Patent number: 10764166Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.Type: GrantFiled: August 21, 2018Date of Patent: September 1, 2020Assignee: International Business Machines CorporationInventors: Dirk Allmendinger, Carsten Greiner, Roopesh Ambalath Matayambath, Juergen Ruf
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Patent number: 10678974Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: GrantFiled: October 26, 2017Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Patent number: 10572617Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: GrantFiled: October 26, 2017Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20190094299Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: ApplicationFiled: September 25, 2017Publication date: March 28, 2019Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Publication number: 20190094300Abstract: It is determined, if a simulated hardware signal of a design for an electronic circuit has an influence on a checker for simulation errors. To achieve this, a checker control flow database is generated for a static code description containing checkers and concerned simulated signals. Further, a database based on the output of instrumented verification code is generated, thus gaining dynamic information about the verification code. Herein, the hardware signal values will be associated with colored values or, alternatively, attributed values. For the checkers in the checker control flow database, a list of attributes is generated and stored. Based on the above operations, a hardware signal database is generated, wherein hardware signals are mapped to a list of checkers, based on determining, for each checker in the checker database, the associated hardware signals from its list of attributed values.Type: ApplicationFiled: November 8, 2017Publication date: March 28, 2019Inventors: Carsten Greiner, Minh Cuong Tran, Gerrit Koch, Joerg Walter
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Publication number: 20180359168Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Inventors: Dirk Allmendinger, Carsten Greiner, Roopesh Ambalath Matayambath, Juergen Ruf
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Patent number: 10091080Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.Type: GrantFiled: November 7, 2014Date of Patent: October 2, 2018Assignee: International Business Machines CorporationInventors: Dirk Allmendinger, Carsten Greiner, Roopesh Ambalath Matayambath, Juergen Ruf
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Patent number: 9934343Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: GrantFiled: May 27, 2016Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Patent number: 9928321Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: GrantFiled: October 14, 2016Date of Patent: March 27, 2018Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20180046743Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: October 26, 2017Publication date: February 15, 2018Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20180046742Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: October 26, 2017Publication date: February 15, 2018Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20170344679Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: October 14, 2016Publication date: November 30, 2017Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Publication number: 20170344684Abstract: A method for verification of a design of an electronic circuit is provided. The method includes executing test runs of the design. The method further includes increasing a fail counter if the executing of a test run of the test runs failed. The method further includes increasing a pass counter if the executing of the test run of the test runs passed. The method further includes halting the executing of the test runs of the design if the current ratio of the fail counter versus the pass counter exceeds a predetermined threshold.Type: ApplicationFiled: May 27, 2016Publication date: November 30, 2017Inventors: Carsten Greiner, Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann
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Patent number: 9288161Abstract: Verifying the functionality of an integrated circuit, the integrated circuit being operable for processing a data packet thereby generating a data processing result. A data packet to be processed is evaluated to determine if the data packet is an erroneous data packet. If the data packet is identified as an erroneous data packet, a modified data packet is generated by modifying the erroneous data packet and providing the modified data packet to the integrated circuit. A determination is made as to whether the data processing result comprises the modification; and a malfunction of the integrated circuit is signaled, if the data processing result comprises the modification.Type: GrantFiled: November 26, 2012Date of Patent: March 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Matayambath Roopesh Ambalath, Carsten Greiner, Senthil K. Jayaraj, Juergen Ruf
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Patent number: 9069574Abstract: A computer program product and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.Type: GrantFiled: December 11, 2013Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf
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Publication number: 20150131456Abstract: Testing a packet sequence number checker. The packet sequence number checker may check a packet-based data communication between two interconnected devices. An error injector may be provided in-between the interconnected devices such that the data packets may be received from one of the two interconnected devices and may be sent to the other one of the two interconnected devices by the error injector. A received packet is randomly selected from a packet data stream between the two interconnected devices and stored in a buffer. A length of a later received data packet from the same sender of the two interconnected devices is compared with the selected buffered data packet, and the later received data packet is replaced by the selected buffered data packet.Type: ApplicationFiled: November 7, 2014Publication date: May 14, 2015Inventors: Dirk Allmendinger, Carsten Greiner, Roopesh Ambalath Matayambath, Juergen Ruf
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Patent number: 9026968Abstract: To assist verification of a digital circuit design, a data processing system presents, within a graphical user interface of a display device, a presentation including a plurality of verification notifications arising from verification of a digital circuit design. The data processing system detects one or more user operations by which a user interacts with the plurality of verification notifications utilizing one or more user input devices and stores, in a memory, user operation information regarding the one or more user operations detected by the data processing system. The data processing system determines, based on said user operation information, a recommended subsequent user operation and presents, within the graphical user interface, an indication of the recommended subsequent user operation.Type: GrantFiled: February 27, 2014Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Carsten Greiner, Gerrit Koch, Juergen Ruf, Ken Werner
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Patent number: 9015685Abstract: A method, computer program product, and computer system for analyzing code to improve efficiency of simulating a hardware system. A computer identifies one or more functions calling an application programming interface of a hardware simulator simulating the hardware system. In response to determining that left hand sides of respective one or more Boolean expressions are associated with the one or more functions calling the application programming interface and right hand sides are not associated with the one or more functions calling the application programming interface, the computer identifies the respective one or more Boolean expressions as one or more improvement points in source code for verifying a hardware model of the hardware system.Type: GrantFiled: March 1, 2013Date of Patent: April 21, 2015Assignee: International Business Machines CorporationInventors: Carsten Greiner, Joerg Kayser, Roopesh A. Matayambath, Juergen M. Ruf