Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.

Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.

Abstract: Methods of determining an amount and/or a thickness of residual material in a via based on LL-BSE images of the material are disclosed. Embodiments include etching a plurality of vias through at least one material layer on a wafer; loading the wafer with predetermined measurement parameters in a CD-SEM; acquiring an image of each via of interest using LL-BSE imaging; quantifying grey level values of the images; characterizing residuals of the at least one material layer in each via based on the grey level values; determining an etching success rate based on the characterizing of the residuals; adjusting the etching based on the determining of the etching success rate; and repeating the steps of acquiring, quantifying, characterizing, determining, and adjusting until a desired etching success rate is achieved.

Abstract: Methods of determining an amount and/or a thickness of residual material in a via based on LL-BSE images of the material are disclosed. Embodiments include etching a plurality of vias through at least one material layer on a wafer; loading the wafer with predetermined measurement parameters in a CD-SEM; acquiring an image of each via of interest using LL-BSE imaging; quantifying grey level values of the images; characterizing residuals of the at least one material layer in each via based on the grey level values; determining an etching success rate based on the characterizing of the residuals; adjusting the etching based on the determining of the etching success rate; and repeating the steps of acquiring, quantifying, characterizing, determining, and adjusting until a desired etching success rate is achieved.

Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.

Abstract: A method of the detection of particle contamination on a semiconductor wafer is provides which includes examining an area of the semiconductor wafer by a metrology system comprising a scatterometry or ellipsometry/reflectometry tool to obtain measured metrology data, comparing the measured metrology data with reference metrology data and determining the presence of particle contamination in the examined area of the semiconductor wafer based on the comparison of the measured metrology data with the reference metrology data.

Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.

Abstract: A method of the detection of particle contamination on a semiconductor wafer is provides which includes examining an area of the semiconductor wafer by a metrology system comprising a scatterometry or ellipsometry/reflectometry tool to obtain measured metrology data, comparing the measured metrology data with reference metrology data and determining the presence of particle contamination in the examined area of the semiconductor wafer based on the comparison of the measured metrology data with the reference metrology data.

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining raw measurement data for a wafer of semiconductor material from a metrology tool and adjusting a measurement model utilized by a metrology tool based at least in part on the raw measurement data and a value for a design parameter. The wafer has that value for the design parameter and an attribute of the semiconductor device structure fabricated thereon, wherein the measurement model is utilized by the metrology tool to convert the raw measurement data to a measurement value for the attribute.

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.

Abstract: Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information.

Abstract: A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively.

Abstract: A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.

Abstract: A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.

Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.

Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.

Abstract: By performing at least one additional wet chemical etch process in the edge region and in particular on the bevel of a substrate during the formation of a metallization layer, the dielectric material, especially the low-k dielectric material, may be reliably removed from the bevel prior to the formation of any barrier and metal layers. Moreover, an additional wet chemical etch process may be performed after the deposition of the metal to remove any unwanted metal and barrier material from the edge region and the bevel. Accordingly, defect issues and contamination of substrates and process tools may be efficiently reduced.

Abstract: Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this way, etch non-uniformities, induced by tool non-uniformities and recipe specific characteristics, may be significantly reduced.

Abstract: By performing a wet chemical process after etching a via, contaminations may be removed and a thin passivation layer may be formed that may then be readily removed in a subsequent sputter etch process for forming a barrier/adhesion layer. In a particular embodiment, the wet chemical process may be performed on the basis of fluoric acid and triazole or a compound thereof.