Abstract: A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

Abstract: A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.

Abstract: A test device has an interface for connecting a memory circuit that is to be tested and for receiving fault addresses. The test device further has a fault address memory for storing fault addresses and a control unit for allocating the received fault addresses to a fault address which is to be stored. A first sequence of memory cells can be addressed with a first access time, and a second sequence of memory cells can be addressed with a second access time, in the fault address memory. The second access time is longer than the first access time. First fault addresses are received at a first data rate, and second fault addresses are received at a second data rate, via the interface. The second data rate is lower than the first data rate. The control unit stores the first fault addresses in the fault address memory on the basis of the first sequence of memory cells, and stores the second fault addresses in the fault address memory on a basis of the second sequence of memory cells.

Abstract: The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).

Abstract: The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.

Abstract: A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

Abstract: Arrangement and method for testing a multiplicity of semiconductor chips at the wafer level The invention relates to an arrangement and a method for testing a multiplicity of semiconductor chips (7) at the wafer level, in which an intermediate wiring plane (10) with a global test bus (12) and test pads (11) is applied to the surface of the wafer (6).

Abstract: The invention relates to an integrated circuit having a circuit and a current measuring unit for measuring the current through the functional circuit. The current measuring unit is connected to an output device in order to output the value of the measured current to an external test system via an external connection of the integrated circuit.

Abstract: A data generator for generating test data for a word-oriented semiconductor memory is integrated on a semiconductor chip of the semiconductor memory. The data generator has a shift register.

Abstract: A circuit configuration for trimming reference voltages in semiconductor chips. The circuit configuration contains a test logic unit and a trimming circuit for trimming at the chip level the reference voltages. The reference voltages are compared to an externally supplied comparison voltage and the reference voltage is varied by the trimming circuit if it does not match the comparison voltage.

Abstract: The memory chip has regular memory cells and standby memory cells for replacing faulty memory cells. There is provided a method for checking memory cells of a repaired memory chip, where the memory cells are checked by putting the memory chip into the state before repair. This actuates the memory cells identified as being faulty in spite of the provision of standby memory cells. This allows the operability of the memory chip to be checked after the repair procedure has been carried out. It is thus possible to identify, by way of example, whether a fault has been produced by the repair procedure.

Abstract: A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.

Abstract: A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.

Abstract: The invention relates to a configuration for the measurement of internal voltages in a DUT (2), in which a comparator (3) is provided in each DUT (2) and compares the internal voltage (Vint) to be measured with an externally supplied reference voltage (Vref).

Abstract: A circuit configuration for trimming reference voltages in semiconductor chips. The circuit configuration contains a test logic unit and a trimming circuit for trimming at the chip level the reference voltages. The reference voltages are compared to an externally supplied comparison voltage and the reference voltage is varied by the trimming circuit if it does not match the comparison voltage.