Abstract: The invention describes a passive matrix single-color LED display assembly comprising a matrix of row conductor lines and column conductor lines; an array of direct-emitting LED packages, wherein the anode of each LED package is electrically connected to one of the row conductor lines and the cathode of that LED package is connected to one of the column conductor lines; and a driver configured to apply a bias voltage to a row conductor line and to apply a bias voltage to a column conductor line according to an image to be displayed.

Abstract: The invention describes a method of manufacturing an LED carrier assembly, which method comprises the steps of providing a carrier comprising a mounting surface with mounting pads arranged to receive a number of LED dies; embedding an alignment magnet in the carrier; providing a number of LED dies, wherein an LED die comprises a number of magnetic die pads; and aligning the magnetic die pads to the mounting pads by arranging the LED dies over the mounting surface of the carrier within magnetic range of the alignment magnet. The invention also describes an LED carrier assembly.

Abstract: A lighting arrangement and a method of forming an illumination beam are described. A plurality of LED lighting elements is operable to emit light. A plurality of collimator elements is arranged to collimate light emitted from the LED lighting elements. A first projection element is arranged to project light emitted from the collimator elements onto a spatially controllable reflector element. The spatially controllable element comprises a plurality of reflector elements adjustable between a first and a second position. In the first position, the light is reflected into the direction of a second projection element to form a projected illumination beam. In the second position, light is reflected into a different direction to not contribute to the projected illumination beam.

Abstract: The invention describes a method of manufacturing an LED carrier assembly, which method comprises the steps of providing a carrier comprising a mounting surface with mounting pads arranged to receive a number of LED dies; embedding an alignment magnet in the carrier; providing a number of LED dies, wherein an LED die comprises a number of magnetic die pads; and aligning the magnetic die pads to the mounting pads by arranging the LED dies over the mounting surface of the carrier within magnetic range of the alignment magnet. The invention also describes an LED carrier assembly.

Abstract: The invention describes a passive matrix single-color LED display assembly comprising a matrix of row conductor lines and column conductor lines; an array of direct-emitting LED packages, wherein the anode of each LED package is electrically connected to one of the row conductor lines and the cathode of that LED package is connected to one of the column conductor lines; and a driver configured to apply a bias voltage to a row conductor line and to apply a bias voltage to a column conductor line according to an image to be displayed.

Abstract: A lighting arrangement and a method of forming an illumination beam are described. A plurality of LED lighting elements is operable to emit light. A plurality of collimator elements is arranged to collimate light emitted from the LED lighting elements. A first projection element is arranged to project light emitted from the collimator elements onto a spatially controllable reflector element. The spatially controllable element comprises a plurality of reflector elements adjustable between a first and a second position. In the first position, the light is reflected into the direction of a second projection element to form a projected illumination beam. In the second position, light is reflected into a different direction to not contribute to the projected illumination beam.

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.

Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a heat sink array having a top-side surface and an under-side surface; the heat sink array has die placement areas on the top-side surface. A plurality of active device die are die bonded onto the die placement areas on the heat sink array. The plurality of active device die are singulated into an individual heat sink device die having a heat sink portion attached to its underside.

Abstract: Consistent with an example embodiment, there is a method for packaging an integrated circuit (IC) device. The method comprises attaching a lead frame to the carrier tape; the lead frame has an array of device positions on the carrier tape and pad landings surround the device positions for making electrical connections to the plurality of active device die. A plurality of active device die are mounted on the carrier tape within the array of device positions; each said active device die has bond pads, each of said active device die has been subjected to back-grinding to a prescribed thickness and has a solderable conductive surface on its underside. On the bond pads, the plurality of active devices are wire bonded to the pad landings on the lead frame. The lead frame and wire bonded active devices are encapsulated, leaving the solderable die backside and lead frame backside exposed.

Abstract: In an example embodiment, an integrated circuit (IC) comprises a device die having a top-side surface and an under-side surface, the top-side surface having bond pads connected to active circuit elements, the under-side surface having a conductive surface. A first set of lead frame clips having upper portions and lower portions, are solder-anchored, on the upper portions, to a first set of bond pads; the lower portions are flush with the conductive surface. Wires are bonded to an additional set of bond pads opposite the first set of bond pads and to lower lead frame portions of a second set of lead frame clips opposite the first set of lead frame clips; the lower lead frame portions of the second set of lead frame clips are flush with the conductive surface. The device is encapsulated in a molding compound leaving exposed the conductive surface and underside surfaces of the first and second sets of the lead frame portions.