Patents by Inventor Cass W. Everitt

Cass W. Everitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100001999
    Abstract: A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 7, 2010
    Inventors: Cass W. Everitt, Steven E. Molnar
  • Patent number: 7626588
    Abstract: Prescient cache management methods and systems are disclosed. In one embodiment, a local cache that operates within a raster engine operations stage of a graphics rendering pipeline is managed by following a number of caching decisions related to a number of cached tiles. Each of these cached tiles has a certain priority to remain in the local cache, with the priority corresponding to a conflict type received from a buffer operating within a pre-raster engine operations stage of the graphics rendering pipeline.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: December 1, 2009
    Assignee: NVIDIA Corporation
    Inventors: Steven E. Molnar, Mark J. French, Cass W. Everitt, Adam Clark Weitkemper, Phillip Keslin, David L. Anderson, George R. Lynch
  • Patent number: 7616209
    Abstract: Prescient cache management methods and systems are disclosed. In one embodiment, within a pre-raster engine operations stage in a graphics rendering pipeline, tile entries are stored in a buffer. Each of these tile entries is related a transaction request that enters the pre-raster engine operations stage and has a screen coordinates field and a conflict field. If this buffer includes a first tile entry, which is related to a first transaction request associated with a first tile, and a second tile entry, which is related to a second transaction request that enters the pre-raster engine operations stage after the first transaction request and is also associated with the first tile, the conflict field of the first tile entry is updated with a conflict type that reflects a number of tile entries between the first tile entry and the second tile entry.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: November 10, 2009
    Assignee: NVIDIA Corporation
    Inventors: Steven E. Molnar, Mark J. French, Cass W. Everitt, Adam Clark Weitkemper, Phillip Keslin, David L. Anderson, George R. Lynch
  • Patent number: 7528843
    Abstract: Systems and methods for dynamically canceling texture fetches may improve texture mapping performance. A shader program compiler inserts condition code writes and condition code comparison operations for shader program instructions that contribute to a texture read instruction and do not need to be executed if certain conditions are met. During execution of the shader program, the inserted condition codes are used to compute a dynamic writemask that indicates if the texture data resulting from the texture read is unnecessary. The dynamic writemask is used to cancel unnecessary texture fetches during execution of the shader program.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: May 5, 2009
    Assignee: NVIDIA Corporation
    Inventors: Mark J. Kilgard, Rui M. Bastos, Johnny S. Rhoades, Cass W. Everitt, Wei-Chao Chen
  • Patent number: 7519797
    Abstract: An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is reported asynchronously to a global counter. The global counter is configured to be of higher precision than the local counter and is positioned at a place that is convenient for reporting the events, e.g., at the end of the graphics pipeline.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: April 14, 2009
    Assignee: NIVIDIA Corporation
    Inventors: Gregory J. Stiehl, David L. Anderson, Cass W. Everitt, Mark J. French, Steven E. Molnar
  • Patent number: 7463259
    Abstract: A graphics processing subsystem is programmed with shader programs that make calls to an abstract interface. One or more subshaders implementing the functions of the abstract interface can also be defined. The binding of interfaces to functions is resolved by a language runtime module that compiles the subshaders. As shader programs are compiled, the runtime module determines whether each method call is associated with an interface function. For each interface method call, the runtime module determines the appropriate implementation of the interface to be bound to the method call. Once the appropriate implementation is identified, the interface binding is created using string substitution or indirect addressing instructions. At the time of compilation, which may be during the execution of the rendering application, the desired combinations of subshaders are specified and compiled into a combined shader program, which can then be executed by the graphics processing subsystem.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: December 9, 2008
    Assignee: NVIDIA Corporation
    Inventors: Craig E. Kolb, William R. Mark, Cass W. Everitt, Matthew M. Pharr, Rev Lebaredian
  • Patent number: 7446780
    Abstract: Multisampling techniques provide temporal as well as spatial antialiasing. Coverage for a primitive is be determined at multiple sample locations for a pixel. In one embodiment, coverage is determined using boundary equations representing a boundary surface of the primitive in a three-dimensional space-time. A shading value for the primitive is computed for the pixel and stored for each coverage sample location of the pixel that is covered by the primitive. The sample locations are distributed in both space and time, and multiple sample locations share a single shading computation. The multisampling techniques are extendable to other dimensions that correspond to other image attributes.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: November 4, 2008
    Assignee: NVIDIA Corporation
    Inventors: Cass W. Everitt, Rui M. Bastos
  • Patent number: 7382377
    Abstract: Method and apparatus for processing one or more fragment data. In one embodiment, the method includes processing one or more fragment data to generate one or more texture map addresses for one or more texels, determining relevance information that correspond to the texture map addresses, and translating the relevance information into a rendering constraint data structure.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: June 3, 2008
    Assignee: NVIDIA Corporation
    Inventors: Cass W. Everitt, William P. Newhall, Jr., David B. Glasco
  • Publication number: 20080106552
    Abstract: A virtually-addressed local texture memory stores selected regions (a sparse representation) of a texture for use by a graphics processor. The graphics processor requests a texel of the texture by referencing a virtual address of the texel. A memory interface references an address map to determine whether the requested texel is in one of the regions of the texture that is resident in the local texture memory. If so, the texel is retrieved from the local memory and used in the rendering operation; if not, an alternative texel that is resident in the local memory is retrieved and used in the rendering operation. Non-resident regions that include requested texels are retrieved from a primary texture data store at regular intervals (e.g., once per frame) and stored in local texture memory for use in a subsequent rendering operation.
    Type: Application
    Filed: December 14, 2006
    Publication date: May 8, 2008
    Applicant: NVIDIA Corporation
    Inventor: Cass W. Everitt
  • Patent number: 7355602
    Abstract: Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: April 8, 2008
    Assignee: NVIDIA Corporation
    Inventors: Mark J. Kilgard, Jonah M. Alben, Cass W. Everitt
  • Publication number: 20080068394
    Abstract: A large non-patterned noise texture occupies a relatively small physical memory space. Each of a small set of physical pages in physical memory includes noise texels forming part of a noise texture. A large “virtual” noise texture is created by mapping each one of a large number of pages in virtual address space to one of the small set of physical pages; multiple virtual pages may be mapped to the same physical page. The physical page that each virtual page maps to is randomly or pseudo-randomly selected such that the resulting noise texture appears to be non-repeating. When a noise texel is requested by reference to a virtual address during rendering, the virtual address of the virtual page is translated to the corresponding physical address, and the noise texel is retrieved.
    Type: Application
    Filed: September 15, 2006
    Publication date: March 20, 2008
    Applicant: NVIDIA Corporation
    Inventor: Cass W. Everitt
  • Patent number: 7170513
    Abstract: A system and method are provided for conditional branching in a hardware graphics pipeline. Initially, a plurality of graphics commands is received. Condition data is then affected based on at least some of the graphics commands utilizing the hardware graphics pipeline. At least one of the graphics commands is then conditionally skipping based on the condition data in response to another graphics command utilizing the hardware graphics pipeline.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: January 30, 2007
    Assignee: NVIDIA Corporation
    Inventors: Douglas A. Voorhies, Matthew Craighead, Mark J. Kilgard, Edward Hutchins, Cass W. Everitt
  • Patent number: 7145565
    Abstract: Lights can be conservatively bounded within a depth range. When image pixels are outside of a light's depth range, an associated volume fragment does not have to be rendered. Depth bounds registers can be used to store minimum and maximum depth values for a light. As graphics hardware processes volume fragments overlapping the image, the image's depth values are compared with the values in the depth bounds register. If the image's depth is outside of the depth range for the light, stencil buffer and illumination operations for this volume fragment are bypassed. This optimization can be performed on a per-pixel basis, or simultaneously on a group of adjacent pixels. The depth bounds are calculated from the light, or from the intersection of the volume with one or more other features. A rendering application uses API functions to set the depth bounds for each light and to activate depth bounds checking.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: December 5, 2006
    Assignee: NVIDIA Corporation
    Inventors: Cass W. Everitt, Mark J. Kilgard
  • Patent number: 6989840
    Abstract: A system, method and computer program product are provided for transparency rendering in a graphics pipeline. Initially, colored-transparency information is collected from a plurality of depth layers (i.e. colored-transparency layers, etc.) in a scene to be rendered. The collected colored-transparency information is then stored in memory. The colored-transparency information from the depth layers may then be blended in a predetermined order.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: January 24, 2006
    Assignee: NVIDIA Corporation
    Inventors: Cass W. Everitt, Rui M. Bastos, Mark J. Kilgard
  • Publication number: 20040169651
    Abstract: Lights can be conservatively bounded within a depth range. When image pixels are outside of a light's depth range, an associated volume fragment does not have to be rendered. Depth bounds registers can be used to store minimum and maximum depth values for a light. As graphics hardware processes volume fragments overlapping the image, the image's depth values are compared with the values in the depth bounds register. If the image's depth is outside of the depth range for the light, stencil buffer and illumination operations for this volume fragment are bypassed. This optimization can be performed on a per-pixel basis, or simultaneously on a group of adjacent pixels. The depth bounds are calculated from the light, or from the intersection of the volume with one or more other features. A rendering application uses API functions to set the depth bounds for each light and to activate depth bounds checking.
    Type: Application
    Filed: May 23, 2003
    Publication date: September 2, 2004
    Applicant: NVIDIA Corporation
    Inventors: Cass W. Everitt, Mark J. Kilgard
  • Patent number: 6744433
    Abstract: A system and method are provided for using information from at least one depth layer and for collecting information about at least one additional depth layer utilizing a graphics pipeline. Initially, constraining depth layers are provided which, in turn, define a plurality of depth constraints. Next, a plurality of tests is performed involving the constraining depth layers for collecting information about at least one additional depth layer. The information relating to the at least one depth layer may then be used to improve processing in the graphics pipeline. By the foregoing multiple tests, information relating to a plurality of depth layers may be collected during each of a plurality of rendering passes. Initially, information relating to the constraining depth layers and associated depth constraints is provided in the aforementioned manner. Thereafter, information relating to at least one additional depth layer is collected during additional rendering passes using multiple tests on each rendering pass.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: June 1, 2004
    Assignee: nVidia Corporation
    Inventors: Rui M. Bastos, Cass W. Everitt, Mark J. Kilgard
  • Patent number: 6704025
    Abstract: A system and method are provided for improved shadow mapping in a graphics pipeline. Raw depth values are initially collected from two depth layers in a scene to be rendered. Shadow-map depth values are then calculated utilizing the raw depth values. The scene is then shadow mapped utilizing the shadow-map depth values in order to improve the appearance of shadows in a rendered scene. The various steps are carried out by a hardware-implemented graphics pipeline, which may include texturing or shadowing mapping hardware.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: March 9, 2004
    Assignee: NVIDIA Corporation
    Inventors: Rui M. Bastos, Cass W. Everitt, Mark J. Kilgard