Patents by Inventor Cathal Phelan

Cathal Phelan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
    Patent number: 6363031
    Abstract: An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: March 26, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventor: Cathal Phelan
  • Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
    Publication number: 20010000995
    Abstract: An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.
    Type: Application
    Filed: December 22, 2000
    Publication date: May 10, 2001
    Applicant: CYPRESS SEMICONDUCTOR CORP.
    Inventor: Cathal Phelan
  • Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit
    Patent number: 6166991
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to generate a sleep signal in response to (i) said control signal and (ii) a clock signal.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: December 26, 2000
    Assignee: Cypress Semiconductor Corp.
    Inventor: Cathal Phelan