Patents by Inventor Catherine Bee Liang Ng
Catherine Bee Liang Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9881863Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: February 8, 2017Date of Patent: January 30, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
-
Publication number: 20170148722Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio B. DIMAANO, JR., Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
-
Patent number: 9589875Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: September 9, 2015Date of Patent: March 7, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
-
Publication number: 20150380346Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: September 9, 2015Publication date: December 31, 2015Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
-
Patent number: 9136142Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: April 21, 2014Date of Patent: September 15, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
-
Patent number: 8860079Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.Type: GrantFiled: May 9, 2012Date of Patent: October 14, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
-
Patent number: 8829666Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A support carrier is provided and the at least one die is attached to the support carrier. The first surface of the at least one die is facing the support carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The second surface of the cap is disposed at a different plane than the second surface of the die.Type: GrantFiled: November 14, 2011Date of Patent: September 9, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
-
Publication number: 20140227832Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: United Test and Assembly Center Ltd.Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
-
Patent number: 8716873Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: GrantFiled: July 1, 2011Date of Patent: May 6, 2014Assignee: United Test and Assembly Center Ltd.Inventors: Chuen Khiang Wang, Nathapong Suthiwongsunthorn, Kriangsak Sae Le, Antonio Jr B Dimaano, Catherine Bee Liang Ng, Richard Te Gan, Kian Teng Eng
-
Publication number: 20120220082Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.Type: ApplicationFiled: May 9, 2012Publication date: August 30, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER, LTD.Inventors: Catherine Bee Liang NG, Kriangsak Sae LE, Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN
-
Publication number: 20120119378Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A support carrier is provided and the at least one die is attached to the support carrier. The first surface of the at least one die is facing the support carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The second surface of the cap is disposed at a different plane than the second surface of the die.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Catherine Bee Liang NG, Kriangsak Sae LE, Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN
-
Publication number: 20120001306Abstract: A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads and the second surface includes package contacts. The carrier substrate includes a patterned lead frame which defines a line level with conductive traces and a via level with via contacts. The patterned lead frame provides interconnections between the contact pads and package contacts. The carrier substrate further includes a dielectric layer isolating the conductive traces and via contacts. The device includes a die mounted on the die region of the first surface.Type: ApplicationFiled: July 1, 2011Publication date: January 5, 2012Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Chuen Khiang WANG, Nathapong SUTHIWONGSUNTHORN, Kriangsak SAE LE, Antonio Jr B DIMAANO, Catherine Bee Liang NG, Richard Te GAN, Kian Teng ENG
-
Patent number: 7948095Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.Type: GrantFiled: February 11, 2009Date of Patent: May 24, 2011Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Chin Hock Toh, Anthony Yi-Sheng Sun
-
Publication number: 20100109169Abstract: A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly.Type: ApplicationFiled: April 28, 2009Publication date: May 6, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTDInventors: Ravi Kanth KOLAN, Anthony Yi-Sheng Sun, Chin Hock Toh, Catherine Bee Liang Ng, Xue Ren Zhang
-
Publication number: 20090200662Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.Type: ApplicationFiled: February 11, 2009Publication date: August 13, 2009Applicant: UNITED TEST AND ASSEMBLY CENTER LTDInventors: Catherine Bee Liang Ng, Chih Hock Toh, Anthony Yi-Sheng Sun