Patents by Inventor Catherine Mary Ramsdale

Catherine Mary Ramsdale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reducing defects in electronic switching devices
    Patent number: 8896071
    Abstract: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: November 25, 2014
    Assignee: Plastic Logic Limited
    Inventors: Timothy Von Werne, Catherine Mary Ramsdale, Henning Sirringhaus
  • REDUCING DEFECTS IN ELECTRONIC SWITCHING DEVICES
    Publication number: 20100155708
    Abstract: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.
    Type: Application
    Filed: May 12, 2008
    Publication date: June 24, 2010
    Applicant: PLASTIC LOGIC LIMITED
    Inventors: Timothy Von Werne, Catherine Mary Ramsdale, Henning Sirringhaus
  • Electronic device
    Patent number: 7608476
    Abstract: A technique for high-resolution surface energy assisted patterning of semiconductor active layer islands on top of an array of predefined source-drain electrodes without requiring an additional process step for surface energy patterning.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: October 27, 2009
    Assignee: Plastic Logic Limited
    Inventors: Catherine Mary Ramsdale, Henning Sirringhaus, Timothy Allan Von Werne