Patents by Inventor Cathryn J. Christiansen
Cathryn J. Christiansen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10770407Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: GrantFiled: January 4, 2019Date of Patent: September 8, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, Jr., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Publication number: 20200219826Abstract: An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.Type: ApplicationFiled: January 4, 2019Publication date: July 9, 2020Inventors: Zhuojie Wu, Cathryn J. Christiansen, Erdem Kaltalioglu, Ping-Chuan Wang, Ronald G. Filippi, JR., Eric D. Hunt-Schroeder, Nicholas A. Polomoff
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Patent number: 10475677Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.Type: GrantFiled: August 22, 2017Date of Patent: November 12, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Tian Shen, Anil Kumar, Yuncheng Song, Kong Boon Yeap, Ronald G. Filippi, Jr., Linjun Cao, Seungman Choi, Cathryn J. Christiansen, Patrick R. Justison
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Publication number: 20190067056Abstract: An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.Type: ApplicationFiled: August 22, 2017Publication date: February 28, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Tian Shen, Anil Kumar, Yuncheng Song, Kong Boon Yeap, Ronald G. Filippi, JR., Linjun Cao, Seungman Choi, Cathryn J. Christiansen, Patrick R. Justison
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Patent number: 10109599Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.Type: GrantFiled: December 21, 2016Date of Patent: October 23, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Cathryn J. Christiansen, Anthony K. Stamper, Tom C. Lee, Ian Mccallum-Cook
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Publication number: 20180174982Abstract: An integrated circuit (IC) structure is disclosed. The structure can include: an insulator positioned over a device layer; a capping layer positioned over the insulator; an inter-layer dielectric (ILD) positioned over the capping layer; a first metal wire positioned over the ILD, and outside an active area of the IC structure; a continuous metal crack stop in contact with, and interposed between, the first metal wire and the device layer, such that the continuous metal crack stop extends through at least the insulator, the capping layer, and the ILD; a second metal wire positioned over the ILD, and within the active area of the IC structure; and two vias vertically coupled to each other and interposed between the second metal wire and the device layer, such that the two vias extend through at least the insulator, the capping layer, and the ILD.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Cathryn J. Christiansen, Anthony K. Stamper, Tom C. Lee, Ian Mccallum-Cook
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Publication number: 20180102318Abstract: A compound resistor structure can use multiple electrically conductive pads connected by resistive elements to provide the equivalent resistance of a conventional resistor while spreading generated heat over a larger area. An array of pads and resistive elements can create larger resistances, metal connectors between rows of pads allowing current to flow from a first pad in a first row to a last pad in a last row via pads and resistive elements in each row. Fuses connecting pads in such an array can be included to allow tuning of resistance and/or other electrical properties.Type: ApplicationFiled: October 12, 2016Publication date: April 12, 2018Inventors: Cathryn J. Christiansen, Hanyi Ding, Baozhen Li
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Patent number: 9851397Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.Type: GrantFiled: March 2, 2015Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Fen Chen, Cathryn J. Christiansen, Deborah M. Massey, Prakash Periasamy, Michael A. Shinosky
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Patent number: 9831194Abstract: Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated with the portion of the substrate, an interconnect structure on the active circuit region, and a crackstop extending through the interconnect structure. A groove extends through the interconnect structure to the substrate at a location exterior of the crackstop. A stress-containing layer is formed on at least a portion of the groove.Type: GrantFiled: July 6, 2016Date of Patent: November 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Tom C. Lee, Cathryn J. Christiansen, Ian A. McCallum-Cook, Anthony K. Stamper
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Patent number: 9780031Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.Type: GrantFiled: September 4, 2014Date of Patent: October 3, 2017Assignee: GLOBALFOUDRIES INC.Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne, Charles W. Griffin
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Patent number: 9768065Abstract: Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.Type: GrantFiled: July 6, 2016Date of Patent: September 19, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Ping-Chuan Wang, Erdem Kaltalioglu, Ronald G. Filippi, Cathryn J. Christiansen
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Patent number: 9685370Abstract: Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.Type: GrantFiled: December 18, 2014Date of Patent: June 20, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Jonathan D. Chapple-Sokol, Cathryn J. Christiansen, Jeffrey P. Gambino, Tom C. Lee, William J. Murphy, Anthony K. Stamper
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Publication number: 20160258998Abstract: A system for electromigration testing is disclosed. The system includes a conductive member, a cap layer of insulative material over at least a portion of a top surface of the conductive member, a cathode conductively connected to a first end of the conductive member; an anode conductively connected to a second end of the conductive member, and a current source conductively connected to the cathode and the anode. A plurality of sensory pins are disposed along a length of the conductive member between the first end and the second end of the conductive member. The sensory pins are conductively connected to a bottom surface of the conductive member. At least one measurement device is conductively connected to at least one sensory pin of the plurality of sensory pins. The at least one measurement device determines a resistance of at least one portion of the conductive member.Type: ApplicationFiled: March 2, 2015Publication date: September 8, 2016Inventors: Fen Chen, Cathryn J. Christiansen, Deborah M. Massey, Prakash Periasamy, Michael A. Shinosky
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Patent number: 9435852Abstract: Aspects of the present disclosure provide an integrated circuit (IC) test structure. An IC structure according to the present disclosure can include: a monitor chain having a first end electrically connected to a second end through a plurality of metal wires each positioned within one of a first metal level and a second metal level, wherein the first metal level is vertically separated from the second metal level; a first test wire positioned within the first metal level and extending in a first direction, wherein the first test wire is electrically insulated from the monitor chain; and a second test wire positioned within the second metal level and extending in a second direction, wherein the second test wire is electrically insulated from the monitor chain and the first test wire, and wherein the first direction is different from the second direction.Type: GrantFiled: September 23, 2015Date of Patent: September 6, 2016Assignee: GlobalFoundries, Inc.Inventors: Andrew T. Kim, Cathryn J. Christiansen, Ping-Chuan Wang
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Publication number: 20160181151Abstract: Approaches for providing a liner at a via-to-wire interface are provided. A method includes: forming a via opening that exposes an upper surface of a copper wire; forming a titanium liner on the upper surface of the wire; forming a tungsten liner on the titanium liner; and forming a via on the second liner in the via opening.Type: ApplicationFiled: December 18, 2014Publication date: June 23, 2016Inventors: Jonathan D. Chapple-Sokol, Cathryn J. Christiansen, Jeffrey P. Gambino, Tom C. Lee, William J. Murphy, Anthony K. Stamper
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Publication number: 20160071790Abstract: Wiring structures with dummy metal features and methods of manufacture are disclosed. A structure includes a metal wiring structure, and dummy metal features in electrical and direct physical contact with the metal wiring structure in a same plane as the metal wiring structure. The dummy metal features do not change a resistance of the metal wiring structure and are remote from other structures.Type: ApplicationFiled: September 4, 2014Publication date: March 10, 2016Inventors: Fen CHEN, Cathryn J. CHRISTIANSEN, Roger A. DUFRESNE, Charles W. GRIFFIN
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Patent number: 9214427Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.Type: GrantFiled: May 13, 2015Date of Patent: December 15, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
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Publication number: 20150243601Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.Type: ApplicationFiled: May 13, 2015Publication date: August 27, 2015Inventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner
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Publication number: 20150221567Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.Type: ApplicationFiled: April 17, 2015Publication date: August 6, 2015Inventors: Fen Chen, Cathryn J. Christiansen, Roger A. Dufresne
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Patent number: 9087841Abstract: Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect.Type: GrantFiled: October 29, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: Cathryn J. Christiansen, Andrew H. Norfleet, Kirk D. Peterson, Andrew A. Turner