Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell consisting essentially of one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. The device includes data sense circuitry coupled to the memory cell. The data sense circuitry comprises a word line coupled to the gate region and a bit output coupled to the source region or the drain region.

Abstract: A semiconductor memory cell comprising a transistor having (i) an electrically floating body region and (ii) semiconductor source, drain and/or body regions that are “locally” or “globally” under mechanical strain (for example, strain introduced via tensile or compressive forces). The semiconductor memory cell includes (1) a first data state which corresponds to a first charge in the electrically floating body region of the transistor of the memory cell, and (2) a second data state which corresponds to a second charge in the electrically floating body region of the transistor of the memory cell. The semiconductor memory cell may comprise a portion of an integrated circuit device, for example, logic device (such as, a microcontroller or microprocessor) or a portion of a memory device (such as, a discrete memory). A plurality of such memory cells may be arranged to form a memory cell array.