Patents by Inventor Celeste M. Brown

Celeste M. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157005
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Tony S. Baker, Theodros Yigzaw, Chris Ackles, Celeste M. Brown
  • Publication number: 20180095681
    Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to utilize non-volatile random access memory for information storage in response to error conditions are disclosed. Example methods disclosed herein include accessing, with a power control unit associated with a processor, first information describing available capacities of respective reserved regions of a plurality of non-volatile memory modules, the respective reserved regions of the non-volatile memory modules being separate from respective host-visible regions of the non-volatile memory modules. Disclosed example methods also include configuring, with the power control unit, an information storage architecture based on the first information. Disclosed example methods further include storing, with the power control unit, second information in one or more of the respective reserved regions of the non-volatile memory modules in accordance with the information storage architecture.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Robert C. Swanson, Tony S. Baker, Theodros Yigzaw, Chris Ackles, Celeste M. Brown
  • Patent number: 9141166
    Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan
  • Publication number: 20120185706
    Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 19, 2012
    Inventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan