Patents by Inventor Cesar A. Quiroz

Cesar A. Quiroz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180075174
    Abstract: A system simulation runs in addition to a standard simulator a power estimation block which uses the instrumented representation of the system and live data from the standard simulator to compute power consumption and then to display this on a GUI.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Inventors: NINAD HUILGOL, CESAR QUIROZ
  • Patent number: 9557804
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
  • Publication number: 20160018883
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: Ankush VARMA, Krishnakanth V. SISTLA, Cesar A. QUIROZ, Vivek GARG, Martin T. ROWLAND, Inder M. SODHI, James S. BURNS
  • Patent number: 9158351
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
  • Patent number: 9141166
    Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan
  • Publication number: 20130332753
    Abstract: A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor and memory modules. By expanding the power domain to include the processor and the memory modules, dynamic sharing of the power budget of the platform between the processor and the memory modules is enabled. For low-bandwidth workloads, the dynamic sharing of the power budget offers significant opportunity for the processor to increase its frequency by using the headroom in the memory power and vice versa. This enables higher peak performance for the same total platform power budget in one embodiment of the invention.
    Type: Application
    Filed: March 29, 2012
    Publication date: December 12, 2013
    Inventors: Ankush Varma, Krishnakanth V. Sistla, Cesar A. Quiroz, Vivek Garg, Martin T. Rowland, Inder M. Sodhi, James S. Burns
  • Publication number: 20120185706
    Abstract: An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a control loop period a power interface determines energy consumption of the power domain, intelligently budgets power among devices within the power domain based on the energy consumption, converts those budgets to performance maximums for the power domain, and limits performance of devices in the power domain to the performance maximums utilizing a running average power limit.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 19, 2012
    Inventors: Krishnakanth V. Sistla, Martin T. Rowland, Cesar A. Quiroz, Joseph R. Doucette, Gopikrishna Jandhyala, Kai Cheng, Celeste M. Brown, Avinash N. Ananthakrishnan