Abstract: A shared memory multiprocessor having a packet switched bus, together with write back caches for connecting individual processor to that bus, employs a consistency protocol that permits the caches to store multiple copies of read/write data at identical physical addresses for use as needed by the respective processors. The protocol causes the hardware to automatically and transparently maintain the consistency of this data. To that end, the caches detect when a datum becomes shared by monitoring the traffic on the bus, thereby enabling them to broadcast an updating write on the bus whenever their respective processors issue a write to a shared address. If desired, this protocol may be extended to include an advisory invalidate for reducing the amount of address sharing that occurs, thereby enhancing the efficiency of the protocol. The protocol maintains a consistent view of memory for the processors, while permitting I/O devices to have direct access to the memory system.