Patents by Inventor Cesare TORTI
Cesare TORTI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11798630Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.Type: GrantFiled: August 20, 2021Date of Patent: October 24, 2023Assignee: STMicroelectronics S.r.l.Inventors: Marcella Carissimi, Fabio Enrico Carlo Disegni, Chantal Auricchio, Cesare Torti, Davide Manfre', Laura Capecchi, Emanuela Calvetti, Stefano Zanchi
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Patent number: 11756614Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.Type: GrantFiled: April 4, 2022Date of Patent: September 12, 2023Assignee: STMicroelectronics S.r.l.Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Davide Manfré, Cesare Torti
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Patent number: 11475960Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.Type: GrantFiled: May 3, 2021Date of Patent: October 18, 2022Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.Inventors: Fabio Enrico Carlo Disegni, Laura Capecchi, Marcella Carissimi, Vikas Rana, Cesare Torti
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Publication number: 20220230682Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.Type: ApplicationFiled: April 4, 2022Publication date: July 21, 2022Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Davide Manfré, Cesare Torti
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Patent number: 11380380Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.Type: GrantFiled: November 3, 2020Date of Patent: July 5, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti, Guiseppe Scardino
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Patent number: 11380393Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.Type: GrantFiled: December 21, 2020Date of Patent: July 5, 2022Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Massimo Caruso, Cesare Torti
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Patent number: 11355191Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.Type: GrantFiled: October 16, 2020Date of Patent: June 7, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti
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Patent number: 11328768Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.Type: GrantFiled: December 11, 2020Date of Patent: May 10, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Davide Manfré, Cesare Torti
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Patent number: 11322201Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.Type: GrantFiled: January 27, 2021Date of Patent: May 3, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Michele La Placa, Cesare Torti
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Patent number: 11289158Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.Type: GrantFiled: December 16, 2020Date of Patent: March 29, 2022Assignee: STMICROELECTRONICS S.R.L.Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti, Davide Manfré
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Publication number: 20220068395Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.Type: ApplicationFiled: August 20, 2021Publication date: March 3, 2022Applicant: STMicroelectronics S.r.l.Inventors: Marcella CARISSIMI, Fabio Enrico Carlo DISEGNI, Chantal AURICCHIO, Cesare TORTI, Davide MANFRE', Laura CAPECCHI, Emanuela CALVETTI, Stefano ZANCHI
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Publication number: 20210366554Abstract: An embodiment non-volatile memory device includes an array of memory cells in rows and columns; a plurality of local bitlines, the memory cells of each column being coupled to a corresponding local bitline; a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines; a plurality of program driver circuits, each having a corresponding output node and injecting a programming current in the corresponding output node, each output node coupleable to a corresponding subset of main bitlines. Each program driver circuit further includes a corresponding limiter circuit that is electrically coupled, for each main bitline of the corresponding subset, to a corresponding sense node whose voltage depends, during writing, on the voltage on the corresponding main bitline. Each limiter circuit turns off the corresponding programming current, in case the voltage on any of the corresponding sense nodes overcomes a reference voltage.Type: ApplicationFiled: May 3, 2021Publication date: November 25, 2021Inventors: Fabio Enrico Carlo Disegni, Laura Capecchi, Marcella Carissimi, Vikas Rana, Cesare Torti
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Publication number: 20210233582Abstract: An embodiment voltage generation circuit, for a memory having a memory array with a plurality of memory cells coupled to respective wordlines and local bit-lines, each having a storage element and selector element, a bipolar transistor being coupled to the storage element for selective flow of a cell current during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bit-line is a biasing transistor having a control terminal, and the circuit generates a cascode voltage for this control terminal; a driver stage is coupled to one end of each wordline. The circuit generates the cascode voltage based on a reference voltage, which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.Type: ApplicationFiled: January 27, 2021Publication date: July 29, 2021Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Michele La Placa, Cesare Torti
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Patent number: 11049561Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.Type: GrantFiled: June 16, 2020Date of Patent: June 29, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Fabio Enrico Carlo Disegni, Federico Goller, Cesare Torti, Marcella Carissimi, Emanuela Calvetti
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Publication number: 20210193220Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.Type: ApplicationFiled: December 11, 2020Publication date: June 24, 2021Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Davide Manfré, Cesare Torti
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Publication number: 20210193221Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.Type: ApplicationFiled: December 21, 2020Publication date: June 24, 2021Inventors: Maurizio Francesco Perroni, Fabio Enrico Carlo Disegni, Massimo Caruso, Cesare Torti
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Publication number: 20210183442Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.Type: ApplicationFiled: December 16, 2020Publication date: June 17, 2021Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti, Davide Manfré
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Publication number: 20210166745Abstract: A non-volatile memory device including an array of memory cells coupled to word lines and a row decoder, which includes a first and a second pull-down stage, which are arranged on opposite sides of the array, and include, respectively, for each word line, a corresponding first pull-down switching circuit and a corresponding second pull-down switching circuit, which are coupled to a first point and a second point, respectively, of the first word line. The row decoder moreover comprises a pull-up stage, which includes, for each word line, a corresponding pull-up switching circuit, which can be electronically controlled in order to: couple the first point to a supply node in the step of deselection of the word line; and decouple the first point from the supply node in the step of selection of the word line.Type: ApplicationFiled: November 3, 2020Publication date: June 3, 2021Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti, Guiseppe Scardino
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Publication number: 20210125668Abstract: An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.Type: ApplicationFiled: October 16, 2020Publication date: April 29, 2021Inventors: Fabio Enrico Carlo Disegni, Maurizio Francesco Perroni, Cesare Torti
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Publication number: 20200411092Abstract: A method for programming a phase-change-memory device of a differential type comprises, in a first programming mode, supplying, during a first time interval, a same first programming current, of a type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said first programming current; and, in a second programming mode, supplying, during a second time interval, a same second programming current, of the other type chosen between a SET current and a RESET current, to all the direct and complementary memory cells that are to be programmed with said second programming current, thus completing, in just two time steps, writing of a logic word in the memory device.Type: ApplicationFiled: June 16, 2020Publication date: December 31, 2020Inventors: Fabio Enrico Carlo Disegni, Federico Goller, Cesare Torti, Marcella Carissimi, Emanuela Calvetti