Patents by Inventor Cha-Jea Jo
Cha-Jea Jo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170229412Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: ApplicationFiled: April 24, 2017Publication date: August 10, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Seung-kwan RYU, Cha-jea JO, Tae-Je CHO
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Patent number: 9728424Abstract: A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.Type: GrantFiled: May 28, 2015Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hwang Kim, Un-byoung Kang, Cha-jea Jo, Tae-je Cho
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Publication number: 20170170136Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: ApplicationFiled: August 15, 2016Publication date: June 15, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sun-kyoung SEO, Seung-kwan RYU, Cha-jea JO, Tae-Je CHO
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Patent number: 9666551Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.Type: GrantFiled: August 15, 2016Date of Patent: May 30, 2017Assignee: Smasung Electronics Co., Ltd.Inventors: Sun-kyoung Seo, Seung-kwan Ryu, Cha-jea Jo, Tae-Je Cho
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Patent number: 9618716Abstract: A photonic integrated circuit is provided. The photonic integrated circuit includes a substrate having a through hole interconnecting a first surface and a second surface; a transmission wire passing through the through hole and including an optical transmission structure and an electrical transmission structure; and an optical-to-electrical converter connected to the optical transmission structure of the transmission wire on the first surface.Type: GrantFiled: January 5, 2016Date of Patent: April 11, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sang-Cheon Park, Cha-Jea Jo, Tae-Je Cho
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Patent number: 9589945Abstract: A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.Type: GrantFiled: July 21, 2015Date of Patent: March 7, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Cha-jea Jo, Yun-hyeok Im, Tae-je Cho
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Publication number: 20170047310Abstract: A semiconductor package may include a package substrate, a semiconductor chip and a molding member. A protrusion may be formed on a side surface of the package substrate. The semiconductor chip may be arranged on an upper surface of the package substrate. The semiconductor chip may be electrically connected with the package substrate. The molding member may be formed on the upper surface and the side surface of the package substrate, and an upper surface of the protrusion. Thus, the molding member on the protrusion of the package substrate may be configured to cover the side surface of the package substrate so that the side surface of the package substrate may not be exposed.Type: ApplicationFiled: June 15, 2016Publication date: February 16, 2017Inventors: Jong-Bo SHIM, Seung-Duk BAEK, Cha-Jea JO, Tae-Je CHO
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Patent number: 9543231Abstract: Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.Type: GrantFiled: January 14, 2015Date of Patent: January 10, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yun-seok Choi, Hyeok-man Kwon, Cha-jea Jo, Tae-je Cho
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Publication number: 20160266341Abstract: A photonic integrated circuit is provided. The photonic integrated circuit includes a substrate having a through hole interconnecting a first surface and a second surface; a transmission wire passing through the through hole and including an optical transmission structure and an electrical transmission structure; and an optical-to-electrical converter connected to the optical transmission structure of the transmission wire on the first surface.Type: ApplicationFiled: January 5, 2016Publication date: September 15, 2016Inventors: Sang-Cheon PARK, Cha-Jea JO, Tae-je CHO
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Publication number: 20160225721Abstract: A semiconductor package having an upper surface, a lower surface, and at least one side surface is provided. The semiconductor package includes a mold member disposed on the upper surface and at least one side surface of a semiconductor chip included in the semiconductor package. A marking pattern in the semiconductor package having information about the semiconductor chip is formed on at least one side surface of the mold member.Type: ApplicationFiled: December 3, 2015Publication date: August 4, 2016Inventors: EUN-KYOUNG CHOI, SANG-UK HAN, CHA-JEA JO, TAE-JE CHO
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Publication number: 20160093598Abstract: A semiconductor package includes a package base substrate, at least one first semiconductor chip disposed on the package base substrate, and at least one stacked semiconductor chip structure disposed on the package base substrate adjacent to the at least one first semiconductor chip. The at least one stacked semiconductor chip includes a plurality of second semiconductor chips. A penetrating electrode region including a plurality of penetrating electrodes is disposed adjacent to an edge of the at least one stacked semiconductor chip structure.Type: ApplicationFiled: July 21, 2015Publication date: March 31, 2016Inventors: Cha-jea JO, Yun-hyeok IM, Tae-je CHO
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Publication number: 20160013091Abstract: A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.Type: ApplicationFiled: May 28, 2015Publication date: January 14, 2016Inventors: Ji-hwang Kim, Un-byoung Kang, Cha-jea Jo, Tae-je Cho
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Patent number: 9159659Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.Type: GrantFiled: March 15, 2013Date of Patent: October 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Won Kim, Kwang-Chul Choi, Hyun-Jung Song, Cha-Jea Jo, Eun-Kyoung Choi, Ji-Seok Hong
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Publication number: 20150200154Abstract: Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip.Type: ApplicationFiled: January 14, 2015Publication date: July 16, 2015Inventors: Yun-seok CHOI, Hyeok-man KWON, Cha-jea JO, Tae-je CHO
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Publication number: 20150162265Abstract: Semiconductor packages including chips having through silicon vias (TSVs) and methods of manufacturing the same may be provided to provide reliable and thinner semiconductor packages by mitigating or preventing a crack from occurring at an uppermost chip. The semiconductor package including a substrate, a first chip stacked on the substrate, the first chip including a plurality of through silicon vias (TSVs), an uppermost chip stacked on the first chip, the uppermost chip being thicker than the first chip, a first gap fill portion covering at least a portion of a side surface of the uppermost chip while filling a space between the first chip and the uppermost chip, and a sealant for sealing the first chip, the uppermost chip, and the first gap fill portion may be provided.Type: ApplicationFiled: August 4, 2014Publication date: June 11, 2015Inventors: Cha-Jea JO, Tae-Je CHO
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Patent number: 8980689Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.Type: GrantFiled: November 25, 2013Date of Patent: March 17, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Byoung-Soo Kwak, Cha-Jea Jo, Tae-Je Cho, Sang-Uk Han
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Patent number: 8912048Abstract: A method of fabricating a semiconductor device includes attaching a semiconductor substrate to a carrier using a carrier fixing layer, where the semiconductor substrate including a plurality of semiconductor chips. The method further includes forming gaps between adjacent ones of the chips. The gaps may be formed using one or more chemicals or light which act to remove portions of the semiconductor substrate to expose the carrier fixing layer. Additional portions of the carrier fixing layer are then removed to allow for removal of the chips from the carrier.Type: GrantFiled: March 14, 2013Date of Patent: December 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Youn Kim, Ji-Hwang Kim, Hae-Jung Yu, Cha-Jea Jo
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Publication number: 20140273350Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.Type: ApplicationFiled: November 25, 2013Publication date: September 18, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: BYOUNG-SOO KWAK, CHA-JEA JO, TAE-JE CHO, SANG-UK HAN
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Publication number: 20140252605Abstract: Provided are a semiconductor package and a method of fabricating the same. The method of fabricating the semiconductor package includes arranging each of a plurality of second semiconductor chips and each of a plurality of first semiconductor chips to be electrically connected to each other on a first wafer which includes the plurality of first semiconductor chips, with a first width of each of the first semiconductor chips is greater than a second width of each of the second semiconductor chips, forming a first molding layer surrounding the second semiconductor chips on the first wafer, forming a chip package including the first and second semiconductor chips by sawing the first wafer in units of the first semiconductor chips, arranging the chip package on a package substrate to electrically connect the second semiconductor chips to the package substrate, and forming a second molding layer surrounding the chip package on the package substrate.Type: ApplicationFiled: March 6, 2014Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Keum-Hee MA, Cha-Jea JO, Sang-Uk HAN
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Publication number: 20140239478Abstract: A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.Type: ApplicationFiled: March 14, 2013Publication date: August 28, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Seok HONG, Sang-Uk HAN, Eun-Kyoung CHOI, Jong-Youn KIM, Hae-Jung YU, Cha-Jea JO