Patents by Inventor Chad M. Burke
Chad M. Burke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10020256Abstract: A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.Type: GrantFiled: January 19, 2015Date of Patent: July 10, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 9224640Abstract: Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.Type: GrantFiled: August 17, 2012Date of Patent: December 29, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20150130019Abstract: A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.Type: ApplicationFiled: January 19, 2015Publication date: May 14, 2015Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 8999767Abstract: A method including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the seed layer causing the seed layer to reflow and fill the first via opening, fill the second via opening, and partially fill the trench opening to form a first via, a second via, and a fuse line, respectively, wherein the seed layer no longer remains along an entire length of a sidewall of the trench opening. The method further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.Type: GrantFiled: January 31, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20140210041Abstract: An electronic fuse structure including etching a dual damascene feature in a dielectric layer, the dual damascene feature including a first via opening, a second via opening, and a trench opening, forming a seed layer within the dual damascene feature, the seed layer including a conductive material, and heating the dielectric layer and the seed layer causing the seed layer to reflow and fill the first via opening, the second via opening, and partially filling the trench opening to form a fuse line, a first via, and a second via. The structure further including forming an insulating layer on top of the fuse line, and forming a fill material on top of the insulating layer and substantially filling the trench opening.Type: ApplicationFiled: January 31, 2013Publication date: July 31, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
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Publication number: 20140048927Abstract: Structure and methods for forming a semiconductor structure. The semiconductor structure includes a plurality of layers comprising at least one copper interconnect layer. The copper interconnect layer provides an electrical conduit between one of physically adjacent layers in the semiconductor structure and an integrated circuit in the semiconductor structure and an electronic device. A plurality of studs is positioned within the at least one copper interconnect layer. The studs are spaced apart by a distance less than or equal to a Blech length of the at least one copper interconnect layer. The Blech length is a length below which damage due to electromigration of metal atoms within the at least one copper interconnect layer does not occur. The plurality of studs comprises copper atom diffusion barriers.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: International Business Machines CorporationInventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 8232809Abstract: Solutions for determining a critical current density of a line are disclosed. In one embodiment a method of determining a critical current density in a line includes: applying a temperature condition to each of a plurality of samples including the line; calculating a cross-sectional area of the line for each of the plurality samples using data about an electrical resistance of the line over each of the temperature conditions; measuring an electrical current reading through the line for each of the plurality of samples; determining a current density through the line for each of the plurality of samples by dividing each electrical current reading by each corresponding cross-sectional area; determining an electromigration (EM) failure time for each of the plurality of samples; and determining the critical current density of the line using the current density and the plurality of EM failure times.Type: GrantFiled: November 18, 2009Date of Patent: July 31, 2012Assignee: International Business Machines CorporationInventors: Chad M. Burke, Cathryn J. Christiansen, Baozhen Li
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Publication number: 20110115508Abstract: Solutions for determining a critical current density of a line are disclosed. In one embodiment a method of determining a critical current density in a line includes: applying a temperature condition to each of a plurality of samples including the line; calculating a cross-sectional area of the line for each of the plurality samples using data about an electrical resistance of the line over each of the temperature conditions; measuring an electrical current reading through the line for each of the plurality of samples; determining a current density through the line for each of the plurality of samples by dividing each electrical current reading by each corresponding cross-sectional area; determining an electromigration (EM) failure time for each of the plurality of samples; and determining the critical current density of the line using the current density and the plurality of EM failure times.Type: ApplicationFiled: November 18, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad M. Burke, Cathryn J. Christiansen, Baozhen Li