Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: Hardware accelerated synchronization of data movement across multiple direct memory access (DMA) engines is provided using techniques in which the order of descriptor processing is guaranteed for scenarios involving a single CPU and multiple DMA engines as well as those involving multiple CPUs and multiple DMA engines.

Abstract: The invention relates to an embroidery frame and a frame cover configured to mate with the fabric frame and align a fabric frame opening with a frame cover opening to provide a single embroidery frame opening, where the frame cover has a plurality of engagement members adapted to releasably engage the fabric frame and cover the gripper strips.

Abstract: In a first aspect, a first method is provided for controlling the flow of data between a first and second clock domain. The first method includes the steps of (1) selecting one of a plurality of ports included in a physical layer interface in the second clock domain to which to send data; and (2) transmitting data from a transmit buffer in the first clock domain to the selected port in the physical layer interface in the second clock domain. Numerous other aspects are provided.

Abstract: An apparatus, program product and method utilize a clustering algorithm based upon trading propensity to generate assignments of circuit elements to clusters or groups to optimize a spatial distribution of the plurality of clusters. For example, trading propensity-based clustering may be used to assign circuit elements such as scan-enabled latches to individual scan chains to optimize the layout of the scan chains in a scan architecture for an integrated circuit design.

Abstract: Embodiments of the present invention generally provide an improved technique to handle I/O address translation cache misses caused by I/O commands within a CPU. For some embodiments, CPU hardware may buffer I/O commands that cause an I/O address translation cache miss in a command queue until the I/O address translation cache is updated with the necessary information. When the I/O address translation cache has been updated, the CPU may reissue the I/O command from the command queue, translate the address of the I/O command at a convenient time, and execute the command as if a cache miss did not occur. This way the I/O device does not need to handle an error response from the CPU, the I/O command is handled by the CPU, and the I/O command is not discarded.

Abstract: The present invention provides an improved way to calculate a replacement way within a processor cache that is effective with different combinations of hardware address translation cache miss handling, software address translation cache miss handling, and hint lock bits. For some embodiments, LRU bits used to select an entry for replacement are updated only if software address translation cache miss handling is disabled.

Abstract: An apparatus, program product and method automatically back annotate a functional definition of a circuit design based upon the physical layout generated from the functional definition. A circuit design may be back annotated, for example, by generating a plurality of assignments between a plurality of circuit elements in the circuit design and a plurality of signals defined for the circuit design using a physical definition of the circuit design that has been generated from the functional definition, and modifying the functional definition of the circuit design to incorporate the plurality of assignments into the functional definition.

Abstract: An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to individual scan chains using heuristic clustering to optimize the layout of the scan chains in a scan architecture for a circuit design.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling multiple translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs while an outstanding miss is being handled, the pipeline may be stalled and the command causing the second miss and all subsequent commands may be processed again after the first miss is handled.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. If address translation entries for a command are not found, the translation entries may be retrieved from memory. Address translations for subsequent commands depending from the command getting the miss may be preserved until the address translation entry is retrieved from memory. Therefore, retranslation of addresses for subsequent commands is avoided.

Abstract: Embodiments of the present invention provide methods and systems for maintaining command order while processing commands in a command queue while handling translation cache misses. Commands may be queued in an input command queue at the CPU. During address translation for a command, subsequent commands may be processed to increase efficiency. Processed commands may be placed in an output queue and sent to the CPU in order. During address translation, if a translation cache miss occurs the relevant translation cache entries may be retrieved from memory. After the relevant entries are retrieved a notification may be sent requesting reissue of the command getting the translation cache miss.

Abstract: A method and apparatus for allowing multiple devices access to an address translation cache while cache maintenance operations are occurring at the same time. By interleaving the commands requiring address translation with maintenance operations that may normally take many cycles, address translation requests may have faster access to the address translation cache than if maintenance operations were allowed to stall commands requiring address translations until the maintenance operation was completed.

Abstract: A method and apparatus for the prevention of unwanted access to secure areas of memory during the POR or boot sequence of a CPU. Via control within the CPU, commands that are sent to and received by the CPU prior to the finish of the POR sequence can be denied I/O address translation, thus protecting memory during the POR sequence. Furthermore, an error response can be generated in the CPU and sent back to the I/O device which issued the command.

Abstract: Methods and apparatus for tracking dependencies of commands to be executed by a command processor are provided. By determining the dependency of incoming commands against all commands awaiting execution, dependency information can be stored in a dependency scoreboard. Such a dependency scoreboard may be used to determine if a command is ready to be issued by the command processor. The dependency scoreboard can also be updated with information relating to the issuance of commands, for example, as commands complete.

Abstract: Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.