Abstract: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

Abstract: Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.

Abstract: An apparatus is provided for depositing a thin film. The apparatus includes a chamber, a susceptor disposed in the chamber and supporting a substrate, a reflection housing disposed outside the chamber, a light source unit disposed in the reflection housing and irradiating light to the susceptor, and a light controlling unit blocking at least a portion of an irradiation path of the light to control an irradiation area of the light on the susceptor. At least a portion of the light controlling unit is disposed in the reflection housing.

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

Abstract: An apparatus is provided for depositing a thin film. The apparatus includes a chamber, a susceptor disposed in the chamber and supporting a substrate, a reflection housing disposed outside the chamber, a light source unit disposed in the reflection housing and irradiating light to the susceptor, and a light controlling unit blocking at least a portion of an irradiation path of the light to control an irradiation area of the light on the susceptor. At least a portion of the light controlling unit is disposed in the reflection housing.

Abstract: A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

Abstract: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

Abstract: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

Abstract: A semiconductor memory device includes a stack including gate electrodes and insulating layers that are alternately and repeatedly stacked on a substrate. A cell channel structure penetrates the stack. The cell channel structure includes a first semiconductor pattern contacting the substrate and a first channel pattern on the first semiconductor pattern. The first semiconductor pattern extends to a first height from a surface of the substrate to a top surface of the first semiconductor pattern. A dummy channel structure on the substrate and spaced apart from the stack. The dummy channel structure includes a second semiconductor pattern contacting the substrate and a second channel pattern on the second semiconductor pattern. The second semiconductor pattern extends to a second height from the surface of the substrate to a top surface of the second semiconductor pattern. The first height is greater than the second height.

Abstract: A three-dimensional semiconductor device may include a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes stacked on the substrate to extend from the cell array region to the word line contact region, a channel hole penetrating the gate electrodes on the cell array region and exposing an active region of the substrate, a dummy hole penetrating the gate electrodes on the word line contact region and exposing a device isolation layer provided on the substrate, and a semiconductor pattern provided in the channel hole but not in the dummy hole.

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract: A method of fabricating a three-dimensional (3D) semiconductor memory device is provided. Sacrificial layers and insulating layers are alternately and repeatedly stacked on a top surface of a substrate to form a thin layer structure. A channel structure penetrating the thin layer structure is formed to be in contact with the substrate. A trench penetrating the thin layer structure is formed. The sacrificial layers, the insulating layers and the substrate are exposed in the trench. A recess region formed in the substrate exposed by the trench. A semiconductor pattern filling is formed the recess region. The sacrificial layers exposed by the trench are replaced with gate patterns.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

Abstract: A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.

Abstract: Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

Abstract: A film formation apparatus for a semiconductor process includes a process gas supply system configured to supply process gases. The process gas supply system includes a gas mixture tank configured to mix first and third process gases to form a mixture gas, a mixture gas supply line configured to supply the mixture gas from the gas mixture tank to a process field, a second process gas supply circuit having a second process gas supply line configured to supply a second process gas to the process field without passing through the gas mixture tank, and first and second switching valves disposed on the mixture gas supply line and the second process gas supply line, respectively. A control section controls the first and second switching valves to be opened and closed so as to alternately and pulse-wise supply the mixture gas and the second process gas to the process field.

Abstract: A film formation apparatus for a semiconductor process includes a source gas supply circuit to supply into a process container a source gas for depositing a thin film on target substrates, and a mixture gas supply circuit to supply into the process container a mixture gas containing a doping gas for doping the thin film with an impurity and a dilution gas for diluting the doping gas. The mixture gas supply circuit includes a gas mixture tank disposed outside the process container to mix the doping gas with the dilution gas to form the mixture gas, a mixture gas supply line to supply the mixture gas from the gas mixture tank into the process container, a doping gas supply circuit to supply the doping gas into the gas mixture tank, and a dilution gas supply circuit to supply the dilution gas into the gas mixture tank.

Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a purge gas, a first process gas containing a silane family gas, and a second process gas containing a gas selected from the group consisting of nitriding, oxynitriding, and oxidizing gases. This method alternately includes first to fourth steps. The first, second, third, and fourth steps perform supply of the first process gas, purge gas, second process gas, and purge gas, respectively, while stopping supply of the other two gases. The process field is continuously vacuum-exhausted over the first to fourth steps through an exhaust passage provided with an opening degree adjustment valve. An opening degree of the valve in the first step is set to be 5 to 95% of that used in the second and fourth steps.