Abstract: A data storage device may include: first and second memory devices suitable for sharing an input clock signal line and at least one I/O signal line; and a controller suitable for enabling the first and second memory devices at the same time, and controlling the first and second memory devices by transmitting an input clock signal to the input clock signal line and transmitting an input signal synchronized with the input clock signal to the I/O signal line.

Abstract: A data storage device may include: first and second memory devices suitable for sharing an input clock signal line and at least one I/O signal line; and a controller suitable for enabling the first and second memory devices at the same time, and controlling the first and second memory devices by transmitting an input clock signal to the input clock signal line and transmitting an input signal synchronized with the input clock signal to the I/O signal line.

Abstract: A semiconductor device includes a power-on reset circuit configured to receive a power voltage and generate a power-on reset signal varying with a voltage level of the power voltage, an internal circuit configured to be initialized and operated in response to the power-on reset signal and generate a hold signal based on an operation mode of the internal circuit, and a reset protection circuit configured to deactivate the power-on reset circuit in response to the hold signal and provide a replacement signal for replacing the power-on reset signal to the internal circuit when the power-on reset circuit is deactivated.

Abstract: A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node.

Abstract: A semiconductor device includes a power-on reset circuit configured to receive a power voltage and generate a power-on reset signal varying with a voltage level of the power voltage, an internal circuit configured to be initialized and operated in response to the power-on reset signal and generate a hold signal based on an operation mode of the internal circuit, and a reset protection circuit configured to deactivate the power-on reset circuit in response to the hold signal and provide a replacement signal for replacing the power-on reset signal to the internal circuit when the power-on reset circuit is deactivated.

Abstract: A semiconductor memory device and method of operating the same is disclosed. The semiconductor memory device includes an address decoder including pass transistor groups, a memory block selector coupled in common to the pass transistor groups, and a block decoding section configured to deliver an enable signal through the block word line based on a block group address. The memory block selector is configured to deliver the enable signal to a first pass transistor group selected from the pass transistor groups in response to a block select signal to activate the first pass transistor group.

Abstract: An integrated circuit includes a first internal voltage generation unit configured to generate a first voltage and output the first voltage through an internal voltage terminal in an active operation period, a second internal voltage generation unit configured to generate a second voltage and output the second voltage through the internal voltage terminal in an initial section of a standby operation period, and a third internal voltage generation unit configured to generate a third voltage and output the third voltage through the internal voltage terminal in the remaining section of the standby operation period.

Abstract: A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal.

Abstract: A semiconductor memory device and method of operating the same is disclosed. The semiconductor memory device includes an address decoder including pass transistor groups, a memory block selector coupled in common to the pass transistor groups, and a block decoding section configured to deliver an enable signal through the block word line based on a block group address. The memory block selector is configured to deliver the enable signal to a first pass transistor group selected from the the pass transistor groups in response to a block select signal to activate the first pass transistor group.

Abstract: A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage.

Abstract: A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.

Abstract: A high voltage control circuit of a semiconductor device includes an output node control circuit configured to set an initial potential of an output terminal or to discharge the potential of the output terminal, in response to an input signal and a high voltage supply circuit comprising an acceleration unit and a potential control unit coupled in series between the output terminal and a supply terminal for supplying a high voltage. The acceleration unit is operated in response to the potential of the output terminal, and the potential control unit is operated in response to the input signal.

Abstract: A high voltage switch circuit of a semiconductor device includes a buffer circuit configured to output a control signal in response to an input signal and a boost circuit configured to output a block selection signal to an output terminal by connecting a current path between a voltage supply node and the output terminal in response to the control signal, and to block the current path in case where the control signal falls from a high voltage level to a low voltage level.

Abstract: Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.

Abstract: A pump circuit includes a first clock generation unit, a second clock generation unit and a pumping stage unit. The first clock generation unit is configured to generate a first clock with a first amplitude by using an input clock and an external voltage. The second clock generation unit is configured to generate a second clock with a second amplitude larger than the first amplitude by using the input clock and an amplified voltage generated by amplifying the external voltage. The pumping stage unit is configured to increase an input voltage using the first clock and the second clock and generate amplified output voltages.

Abstract: A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.

Abstract: A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node.

Abstract: A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage.

Abstract: A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.

Abstract: A semiconductor memory apparatus includes: a skew monitoring unit configured to receive a reference voltage and monitor a voltage characteristic of a corresponding MOS transistor; a voltage sensing unit configured to provide a sensing voltage corresponding to the monitoring result of the voltage characteristic; a coding unit configured to multiplex an output signal of the voltage sensing unit and provide a skew control signal; and an internal voltage regulation unit configured to provide an internal voltage by regulating an internal bias voltage in response to the skew control signal.