Patents by Inventor Chaitanya Rajguru

Chaitanya Rajguru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, apparatus, and method to enable and disable a mode of operation of a stacked circuit arrangement on an independent circuit basis using register bits and a single shared mode control line
    Publication number: 20060136755
    Abstract: System, apparatus, and method to enable and disable a mode of operation of a stacked circuit arrangement on an independent circuit basis using register bits and a single shared mode control line.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 22, 2006
    Inventors: Shekoufeh Qawami, Mark Leinwander, Chaitanya Rajguru
  • Non-volatile configuration data storage for a configurable memory
    Publication number: 20060083093
    Abstract: Various embodiments of the invention may provide one or more non-volatile storage entities, such as a register or a storage array, to store configuration information for a memory device. The specified configuration may then be enabled at the occurrence of a specified event, such as power-up and/or reset.
    Type: Application
    Filed: October 15, 2004
    Publication date: April 20, 2006
    Inventors: Lance Dover, Chaitanya Rajguru, Robert Larsen
  • Vcc independent time delay circuit
    Patent number: 6621320
    Abstract: A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant. The time delay circuit also includes a delay element. The output voltage of the first transistor biases the delay element.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: September 16, 2003
    Assignee: Intel Corporation
    Inventors: Waisum Wong, Chaitanya Rajguru
  • Vcc independent time delay circuit
    Publication number: 20020140482
    Abstract: A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant.
    Type: Application
    Filed: March 28, 2001
    Publication date: October 3, 2002
    Inventors: Waisum Wong, Chaitanya Rajguru
  • Method and apparatus for low voltage sensing in flash memories
    Patent number: 6366497
    Abstract: In one embodiment, the invention is an apparatus. The apparatus includes a column load component and a current mirror coupled in parallel with the column load component. The column load component is capable of being coupled to a FLASH cell and a sense amplifier.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Sandeep Guliani, Chaitanya Rajguru, Kedar Mangrulkar