Patents by Inventor Chakrapani Pathikonda

Chakrapani Pathikonda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Core clock correction in a 2/n mode clocking scheme
    Patent number: 6268749
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: July 31, 2001
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Chakrapani Pathikonda, Javed S. Barkatullah
  • Core clock correction in a 2/N mode clocking scheme
    Patent number: 6208180
    Abstract: A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: March 27, 2001
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Chakrapani Pathikonda, Javed S. Barkatullah
  • Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
    Patent number: 6114887
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: November 17, 1997
    Date of Patent: September 5, 2000
    Assignee: Intel Corporation
    Inventors: Chakrapani Pathikonda, Matthew A. Fisch, Michael W. Rhodehamel
  • Method and apparatus for generating 2/N mode bus clock signals
    Patent number: 6104219
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 15, 2000
    Assignee: Intel Corporation
    Inventors: Javed S. Barkatullah, Chakrapani Pathikonda
  • Auto-configuration support for multiple processor-ready pair or FRC-master/checker pair
    Patent number: 6061599
    Abstract: Auto-configuration support for a multiple processor-ready pair or FRC-master/checker pair is achieved through the use of an initialization signal issued to each agent on a bus during system reset. The agents on the bus are interconnected using a rotating interconnect scheme which causes each agent to sample a signal issued from another agent on a pin different from the pin on which the other agent issued the signal. When operating in FRC-master/checker mode, the checker agent operates as if it were the master agent, thereby checking the operation of the master agent. The initialization signal modifies the input and or output lines connected to the pins of the checker agent based on this rotating interconnect scheme, thereby ensuring the checker agent properly checks the master agent's operation.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: May 9, 2000
    Assignee: Intel Corporation
    Inventors: Michael W. Rhodehamel, Nitin V. Sarangdhar, Chakrapani Pathikonda
  • Pad cells for a 2/N mode clocking scheme
    Patent number: 5862373
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: January 19, 1999
    Assignee: Intel Corporation
    Inventors: Chakrapani Pathikonda, Jeff Wight
  • Core clock correction in a 2/N mode clocking scheme
    Patent number: 5834956
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: November 10, 1998
    Assignee: Intel Corporation
    Inventors: Chakrapani Pathikonda, Matthew A. Fisch, Javed S. Barkatullah
  • Method and apparatus for preventing logic glitches in a 2/n clocking scheme
    Patent number: 5826067
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: October 20, 1998
    Assignee: Intel Corporation
    Inventors: Matthew A. Fisch, Chakrapani Pathikonda
  • Method and apparatus for generating 2/N mode bus clock signals
    Patent number: 5821784
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: October 13, 1998
    Assignee: Intel Corporation
    Inventors: Javed S. Barkatullah, Chakrapani Pathikonda
  • Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
    Patent number: 5802132
    Abstract: A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
    Type: Grant
    Filed: September 6, 1996
    Date of Patent: September 1, 1998
    Assignee: Intel Corporation
    Inventors: Chakrapani Pathikonda, Matthew A. Fisch, Michael W. Rhodehamel