Abstract: Disclosed are systems and methods for vehicle charging. A charging system can include a component to convey power to a vehicle to charge the vehicle. The charging system can include a module to store a certificate via a cryptographic technique. The charging system can include a data processing system coupled to the module, the data processing system including one or more processors, coupled with memory, to retrieve the certificate from the module, transmit, to a second data processing system, a request to establish a communication connection, the request including the certificate, and establish the communication connection with the second data processing system responsive to a verification of the certificate by the second data processing system. The data processing system can transmit, to the second data processing system, data corresponding to power conveyed by the component to the vehicle subsequent to verification of the certificate.

Abstract: Disclosed are systems and methods for vehicle charging. A charging system can include a component to convey power to a vehicle to charge the vehicle. The charging system can include a module to store a certificate via a cryptographic technique. The charging system can include a data processing system coupled to the module, the data processing system including one or more processors, coupled with memory, to retrieve the certificate from the module, transmit, to a second data processing system, a request to establish a communication connection, the request including the certificate, and establish the communication connection with the second data processing system responsive to a verification of the certificate by the second data processing system. The data processing system can transmit, to the second data processing system, data corresponding to power conveyed by the component to the vehicle subsequent to verification of the certificate.

Abstract: Methods, systems, and computer storage media for providing energy consumption tracking data based on tracking energy consumption of a charging station for a charging session of an electric vehicle (EV). The energy consumption tracking data can be used to calculate a reimbursement amount for electrical expenses for recharging the EV at a charging station (e.g., charging station at home). Operationally, eligibility data is received at the charging station, the eligibility data identifies an EV as eligible for energy consumption tracking at the charging station. Based on the eligibility data, a determination is made that the EV is eligible for energy consumption tracking to cause tracking energy consumption associated with charging the EV at the charging station. Based on tracking the energy consumption, energy consumption tracking data is generated for the EV at the charging station, and the energy consumption tracking data comprising a calculated energy consumption reimbursement amount is communicated.

Abstract: Systems and methods including a charging station, with one or more processors coupled to memory. The charging station is configured to determine that a first network connection between the charging station and one or more servers is unavailable, detect an electric vehicle having a token within a threshold distance of the charging station, and establish, a second network connection between the charging station and the electric vehicle based the determination that the first network connection is unavailable and the detection of the electric vehicle within the threshold distance. The second channel is encrypted based at least in part on the token provided by the electric vehicle. The charging station is configured to transmit data collected by the charging station to cause the electric vehicle to provide the data to the one or more servers via the second network connection.

Abstract: A system and method for testing a circuit implemented on a programmable logic device. A host processor is coupled to the programmable logic device via an interface device, which has a plurality of signal pins for configuring the programmable logic device. Selected pins of the interface device are connected to selected input pins of the programmable logic device. Test vectors from the host processor are applied to the selected input pins of the programmable logic device via the interface device, and the states of one or more signals appearing on one or more output pins of the device are analyzed.

Abstract: A system and method for testing a circuit implemented on a programmable logic device. A host processor is coupled to the programmable logic device via an interface device, which has a plurality of signal pins for configuring the programmable logic device. Selected pins of the interface device are connected to selected input pins of the programmable logic device. Test vectors from the host processor are applied to the selected input pins of the programmable logic device via the interface device, and the states of one or more signals appearing on one or more output pins of the device are analyzed.

Abstract: A system and method utilize bitmaps for verifying configuration of a programmable logic device (PLD). A configuration bitstream containing configuration commands and data is converted to a configuration bitmap. The configuration bitstream is downloaded to PLD, thus programming the PLD. Readback commands and data read back from the PLD are used to generate a readback bitstream. The readback bitstream is then converted to a readback bitmap. Bits at corresponding cell locations in the readback bitmap and the configuration bitmap are compared. An error signal is output if the bits are different. In one embodiment, a mask bitmap is generated to indicate which cell locations are non-configuration memory cells and thus need not be compared.

Abstract: A system and method for reading back data from a programmable logic device (PLD). A clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative clock cycle at which a selected bit read from the device is saved and sent to a host computer. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset, the bit is selected and saved.