Patents by Inventor Challis L. Purrington

Challis L. Purrington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150347211
    Abstract: One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.
    Type: Application
    Filed: August 11, 2015
    Publication date: December 3, 2015
    Inventors: Tu T. Dang, Michael C. Elles, Juan Q. Hernandez, Dwayne A. Lowe, Challis L. Purrington, SR.
  • Patent number: 9196383
    Abstract: One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: November 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tu T. Dang, Michael C. Elles, Juan Q. Hernandez, Dwayne A. Lowe, Challis L. Purrington, Sr.
  • Patent number: 9040933
    Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 26, 2015
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Milton Cobo, James E. Hughes, Thomas D. Pahel, Jr., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Publication number: 20140191141
    Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 10, 2014
    Applicant: International Business Machines Corporation
    Inventors: MILTON COBO, JAMES E. HUGHES, THOMAS D. PAHEL, JR., PRAVIN S. PATEL, CHALLIS L. PURRINGTON, JACK P. WONG
  • Patent number: 8717030
    Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Milton Cobo, James E. Hughes, Thomas D. Pahel, Jr., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Patent number: 8717031
    Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Milton Cobo, James E. Hughes, Thomas D. Pahel, Jr., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Publication number: 20140013170
    Abstract: One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.
    Type: Application
    Filed: August 27, 2013
    Publication date: January 9, 2014
    Applicant: International Business Machines Corporation
    Inventors: Tu T. Dang, Michael C. Elles, Juan Q. Hernandez, Dwayne A. Lowe, Challis L. Purrington, SR.
  • Patent number: 8554974
    Abstract: Methods, apparatus, and product are disclosed for expanding functionality of hard drive bays in a computing system that include: providing, by a connector in a hard drive bay, access to two or more data communication busses of different type; receiving, by the connector of the hard drive bay, a device mounted within the hard drive bay; and communicately coupling, by the connector of the hard drive bay, the device to one of the data communication busses.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: Warren D. Bailey, James E. Hughes, Thomas D. Pahel, Jr., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Patent number: 8347154
    Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: January 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sumanta K. Bahali, Tu T. Dang, Michael C. Elles, Juan Q. Hernandez, Dwayne A. Lowe, Challis L. Purrington, Michael L. Scollard, Ivan R. Zapata
  • Publication number: 20120235068
    Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.
    Type: Application
    Filed: June 1, 2012
    Publication date: September 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Milton COBO, James E. HUGHES, Thomas D. PAHEL, JR., Pravin S. PATEL, Challis L. PURRINGTON, Jack P. WONG
  • Publication number: 20120126149
    Abstract: Controlling electromagnetic (‘EM’) radiation in a data center having a number EM sections, including: receiving, by an EM controller, a specification of preferred EM radiation characteristics for the data center; and setting, by the EM controller, a state of each EM section in accordance with the specification, where the state of each EM section may be one of: an absorption state in which the EM section absorbs EM radiation or a reflection state in which the EM section reflects EM radiation.
    Type: Application
    Filed: November 18, 2010
    Publication date: May 24, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Milton Cobo, James E. Hughes, Thomas D. Pahel, JR., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Publication number: 20120102367
    Abstract: One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 26, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tu T. Dang, Michael C. Elles, Juan Q. Hernandez, Dwayne A. Lowe, Challis L. Purrington
  • Publication number: 20120072786
    Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 22, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sumanta K. Bahali, Tu T. Dang, Michael C. Elles, Juan Q. Hernandez, Dwayne A. Lowe, Challis L. Purrington, Michael L. Scollard, Ivan R. Zapata
  • Publication number: 20110292591
    Abstract: Methods, apparatus, and product are disclosed for expanding functionality of hard drive bays in a computing system that include: providing, by a connector in a hard drive bay, access to two or more data communication busses of different type; receiving, by the connector of the hard drive bay, a device mounted within the hard drive bay; and communicately coupling, by the connector of the hard drive bay, the device to one of the data communication busses.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Warren D. Bailey, James E. Hughes, Thomas D. Pahel, JR., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Publication number: 20110270814
    Abstract: Methods, apparatus, and product are disclosed for expanding functionality of hard drive bays in a computing system that include: detecting, by a fabric management module, that a new device has been added to a hard drive bay in the computing system; identifying, by the fabric management module, a data communications protocol that is used by the new device; selecting, by the fabric management module, a fabric that supports the data communications protocol that is used by the new device; and routing, by the fabric management module, data communications according to the data communications protocol that is used by the new device across the selected fabric.
    Type: Application
    Filed: April 29, 2010
    Publication date: November 3, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Warren D. Bailey, James E. Hughes, Thomas D. Pahel, JR., Pravin S. Patel, Challis L. Purrington, Jack P. Wong
  • Patent number: 8006028
    Abstract: Methods, systems, and products are disclosed for enabling memory module slots in a computing system after a repair action, the computing system having a plurality of memory module slots and having at least one memory module installed in one of the memory module slots, that includes: determining, during a boot process for the computing system, whether any of the memory module slots are disabled; and if any of the memory module slots are disabled: retrieving, for each memory module installed in one of the memory module slots, a memory module identifier for that memory module, retrieving, from non-volatile memory of the computing system, previously stored memory module identifiers, determining whether the retrieved memory module identifiers match the previously stored memory module identifiers, and enabling the disabled memory module slots if the retrieved memory module identifiers do not match the previously stored memory module identifiers.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: August 23, 2011
    Assignee: International Business Machines Corporation
    Inventors: Tu T. Dang, Robert F. Kantner, Jr., Henry G. McMillan, Carl A. Morrell, Challis L. Purrington, Mark W. Williams
  • Patent number: 7992030
    Abstract: Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: August 2, 2011
    Assignee: International Business Machines Corporation
    Inventors: Henry G. McMillan, Pravin Patel, Challis L. Purrington, Gwendolyn R. Tobin, Christopher C. West, Ivan R. Zapata
  • Patent number: 7971102
    Abstract: Methods, apparatus, and products are disclosed for preemptive thermal management for a computing system based on cache performance, the computing system having a processor, cached computer memory operatively coupled to the processor, and a processor cache operatively coupled to the processor, the processor cache capable of storing a subset of memory contents of the cached computer memory, that include: attempting, by the processor, to retrieve portions of the memory contents of the cached computer memory from the processor cache, resulting in cache misses for the processor cache; tracking, by the processor, cache miss statistics for the processor cache in the computing system, the cache miss statistics describing the cache misses for the processor cache; and administering a thermal management device for the computing system in dependence upon the cache miss statistics, the thermal management device operatively coupled to the processor and capable of managing temperature for the computing system.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Challis L. Purrington, Michael L. Scollard, Victor A. Stankevich, Ivan R. Zapata
  • Patent number: 7954007
    Abstract: The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.
    Type: Grant
    Filed: October 23, 2006
    Date of Patent: May 31, 2011
    Assignee: International Business Machines Corporation
    Inventors: Henry G. McMillan, Christopher C. Moody, Challis L. Purrington, Terry L. Sawyers, Michael L. Scollard, Richard P. Southers, Troy S. Voytko, Christopher C. West, Christopher L. Wood
  • Patent number: 7881064
    Abstract: Flexible paddle cards for installation on a motherboard of a computing system are disclosed that are oriented parallel with the motherboard when installed in the computing system and include: a printed circuit board; and three card connectors that correspond to three motherboard connectors mounted on the motherboard, two of the card connectors mounted on a first rigid region of the printed circuit board, the remaining third card connector mounted on a second rigid region of the printed circuit board, and the first rigid region and the second rigid region separated by a flexible region of the printed circuit board, the flexible region having a width that allows the printed circuit board to flex when the card connectors mate with the motherboard connectors.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dennis F. Cole, Thomas D. Pahel, Jr., Challis L. Purrington, Sean P. Ryan, Jack P. Wong