Abstract: A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address; a delay locked loop (DLL) clock generation unit including a replica configured to have a delay time controlled in response to the delay control signal; and a data output unit configured to output the test data in response to a DLL clock signal outputted from the DLL clock generation unit.

Abstract: An error operation unit configured to output an error detection code in response to a plurality of control signals, a plurality of vectors and data, a vector storage unit configured to store the plurality of vectors, and a vector switching unit configured to provide the plurality of vectors to the error operation unit in response to the plurality of control signals are included.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor memory device. The controller generates a first command signal and receives a foreground data to generate a foreground control signal for controlling a drivability of the foreground data and to generate a second command signal. The semiconductor memory device receives the first command signal to output a pattern data as the foreground data through a foreground input/output (I/O) line, stores the foreground control signal therein in response to the second command signal, and controls the drivability of the foreground data according to the foreground control signal.

Abstract: A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. The temperature code signals are obtained from temperature signals. The internal refresh signal generator outputs a refresh command signal as the internal refresh signal when the first control signal is enabled. Further, the internal refresh signal generator outputs the refresh command signal as the internal refresh signal at a moment that the refresh command signal is inputted thereto by a predetermined number of times when the second control signal is enabled.

Abstract: A semiconductor device including a control signal generator and an internal refresh signal generator is provided. The control signal generator generates first and second control signals, one of which is selectively enabled in response to temperature code signals and mode set signals after a pulse of an internal refresh signal is outputted by the internal refresh signal generator. The temperature code signals are obtained from temperature signals. The internal refresh signal generator outputs a refresh command signal as the internal refresh signal when the first control signal is enabled. Further, the internal refresh signal generator outputs the refresh command signal as the internal refresh signal at a moment that the refresh command signal is inputted thereto by a predetermined number of times when the second control signal is enabled.

Abstract: An error operation unit configured to output an error detection code in response to a plurality of control signals, a plurality of vectors and data, a vector storage unit configured to store the plurality of vectors, and a vector switching unit configured to provide the plurality of vectors to the error operation unit in response to the plurality of control signals are included.

Abstract: Semiconductor systems are provided. The semiconductor system includes a controller and a semiconductor memory device. The controller generates a first command signal and receives a foreground data to generate a foreground control signal for controlling a drivability of the foreground data and to generate a second command signal. The semiconductor memory device receives the first command signal to output a pattern data as the foreground data through a foreground input/output (I/O) line, stores the foreground control signal therein in response to the second command signal, and controls the drivability of the foreground data according to the foreground control signal.

Abstract: A semiconductor memory apparatus includes: a user setting unit configured to generate test data and a delay control signal in response to an external command and an external address; a delay locked loop (DLL) clock generation unit including a replica configured to have a delay time controlled in response to the delay control signal; and a data output unit configured to output the test data in response to a DLL clock signal outputted from the DLL clock generation unit.