Abstract: A storage box having a display panel, which allows an article inside a body to be confirmed from the outside according to an increase in the amount of light caused by an internal light source is disclosed. The storage box having a display panel includes the body and a door including a frame and mounted on the body to be opened and closed, wherein the door includes a glass member provided on a front surface side of the frame, a protective panel provided on an inner surface side of the frame, and a transmittance-variable panel provided between the glass member and the protective panel, the transmittance-variable panel is a panel made of a thermoplastic resin of PMMA or PC and nano-sized dyes, a plurality of nano-sized pores are provided in the transmittance-variable panel.

Abstract: A nonvolatile memory device with high security is provided.

Abstract: One embodiment of the present disclosure provides a condition detection see-through storage box that stores objects, the condition detection see-through storage box including a storage box body configured to store the objects, a sensor configured to detect a specific condition inside the storage box, a door that is installed on the storage box body and has a transmission window, a light emitting module configured to increase an amount of emitted light according to a signal from the sensor, which has detected the specific condition inside the storage box, to increase an amount of light that is reflected from inside the storage box and heads toward the transmission window, and an optical film provided on the transmission window, thereby informing a user of the specific condition inside the storage box body, wherein the optical film has a light transmittance that prevents the storage box from being see-through from the outside before the sensor detects the specific condition and allows the storage box to be see-

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: Provided is a semiconductor memory device. In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor Mary device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.

Abstract: The present disclosure provides a new concept of fusion imaging device for simultaneously providing anatomical information and functional/biochemical information of human bodies, to accurately localize lesions in the pre-operative process and measure in real time, thereby ensuring the stability of patients with lower radiation doses than the existing fusion imaging devices such as positron emission tomography (PET)/computed tomography (CT) and single photon emission computed tomography (SPECT)/CT, and includes: a transducer to transmit and receive an ultrasound; a matching layer positioned on top of the transducer to reduce a difference in acoustic resistance between the transducer and an affected part, to support an ultrasound beam to be smoothly transmitted into tissues and a reflected beam to be received with high sensitivity; a backing member to absorb the ultrasound on an opposite side of the affected part with respect to the transducer; and a scintillator to detect gamma rays which are radiation, wherei

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.

Abstract: A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure disposed on a first substrate, a horizontal semiconductor layer disposed on a second substrate, a plurality of stack structures on the horizontal semiconductor layer in a first direction, wherein the plurality of stack structures include a memory cell region and a capacitor region, a plurality of electrode isolation regions extending in the first direction and a second direction and configured to separate the plurality of stack structures to be connected to the horizontal semiconductor layer and a plurality of through-via structures having a first side connected to a through channel contact through at least one metal pad, wherein a capacitor is formed between each of electrode pads and at least one of electrode isolation regions in the plurality of stack structures or at least one of the plurality of through-via structures.

Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Abstract: A display apparatus includes an oxide semiconductor pattern disposed on a device substrate and including a channel region disposed between a source region and a drain region, a gate electrode overlapping the channel region of the oxide semiconductor pattern and having a structure in which a first hydrogen barrier layer and a gate conductive layer are stacked, and a gate insulating film disposed between the oxide semiconductor pattern and the gate electrode to expose the source region and the drain region of the oxide semiconductor pattern. The gate electrode exposes a portion of the gate insulating film that is adjacent to the source region and a portion of the gate insulating film that is adjacent to the drain region.

Abstract: A display apparatus including a first thin-film transistor, a second thin-film transistor and a third thin-film transistor is provided. The first thin-film transistor includes a first active layer composed of a polysilicon material, a first gate electrode overlapping the first active layer such that a first gate insulating layer is interposed therebetween, a first source electrode and a first drain electrode. The first gate electrode includes n layers. The first source electrode and the first drain electrode are connected to the first active layer. The second thin-film transistor includes a second active layer composed of a polysilicon material, a second gate electrode overlapping the second active layer such that a first gate insulating layer is interposed therebetween, a second source electrode and a second drain electrode. The second gate electrode includes n+1 layers. The second source electrode and the second drain electrode are connected to the second active layer.

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.

Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Abstract: A non-volatile memory includes a first semiconductor layer vertically stacked on a second semiconductor layer and including a first memory group, a second memory group, a third memory group and a fourth memory group. The second semiconductor layer includes a first region, a second region, a third region and a fourth region respectively underlying the first memory group, second memory group, third memory group and fourth memory group. The first region includes one driving circuit connected to memory cells of one of the second memory group, third memory group and fourth memory group through a first word line, and another driving circuit connected to memory cells of the first memory group through a first bit line, wherein the first word line and first bit line extend in the same horizontal direction.

Abstract: A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

Abstract: A three-dimensional (3D) nonvolatile memory includes a stacked structure that includes a plurality of conductive layers that alternate with and are spaced apart from each other by a plurality of interlayer insulating layers. The stacked structure includes a first cell region, a second cell region spaced apart from the first cell region, and a connection region between the first cell region and the second cell region. The connection region includes a first step portion that contacts the first cell region and has a stepped shape that descends in a direction approaching the second cell region, a second step portion that contacts the second cell region and has a stepped shape that descends in a direction approaching the first cell region, and a connection portion that connects the first cell region and the second cell region.

Abstract: A vertical memory device includes a mold structure and channels. The mold structure includes gate electrodes and insulation patterns arranged on a substrate in which the gate electrodes are disposed at a plurality of levels, respectively, in a vertical direction substantially perpendicular to an upper surface of the substrate. The insulation patterns are disposed between neighboring ones of the gate electrodes. The channels extend through the mold structure in the vertical direction in a hole, and are spaced apart from each other in a horizontal direction substantially parallel to the upper surface of the substrate in the hole. The gate electrodes each includes a plurality of first gate electrodes spaced apart from each other substantially horizontally. The hole extends through one of the first gate electrodes included in each of the gate electrodes. A plurality of channels may be formed in the one hole in the one first gate electrode.

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, each including a plurality memory cells coupled to word-lines respectively, and the word-lines are stacked vertically on a substrate. The control circuit divides a first memory block of the plurality of memory blocks into a partial bad region and a partial normal region based on error information of an uncorrectable error of the first memory block which is designated as a bad block. The control circuit performs a memory operation on the partial normal region by applying a first bias condition to the partial bad region and by applying a second bias condition to the partial normal region, based on a command and an address, and the first bias condition is different from the second bias condition.