Patents by Inventor Chan-Long Shieh

Chan-Long Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8742658
    Abstract: A full-color AM OLED includes a transparent substrate, a color filter positioned on an upper surface of the substrate, and a metal oxide thin film transistor backpanel positioned in overlying relationship on the color filter and defining an array of pixels. An array of OLEDs is formed on the backpanel and positioned to emit light downwardly through the backpanel, the color filter, and the substrate in a full-color display. Light emitted by each OLED includes a first emission band with wavelengths extending across the range of two of the primary colors and a second emission band with wavelengths extending across the range of the remaining primary color. The color filter includes for each pixel, two zones separating the first emission band into two separate primary colors and a third zone passing the second emission band.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: June 3, 2014
    Assignee: CBrite Inc.
    Inventors: Gang Yu, Chan-Long Shieh
  • Publication number: 20140138673
    Abstract: A method of fabricating MOTFTs includes positioning opaque gate metal on a transparent substrate, depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Etch stop material is deposited on the semiconductor material. Photoresist defines an isolation area in the semiconductor material. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 22, 2014
    Inventors: Chan- Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20140120640
    Abstract: A method of dispersing semiconductor chips from a wafer of semiconductor chips onto a substrate while preserving the neighboring relationship of each chip to each adjacent chip is disclosed. The method includes dispersing the wafer into sequential columns of semiconductor chips with a first pitch between columns while preserving the neighboring relationship and sequentially dispersing the columns of semiconductor chips into rows of individual chips with a second pitch between rows onto a substrate while preserving the neighboring relationship.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Inventors: Chan- Long Shieh, Gang Yu
  • Patent number: 8679905
    Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 25, 2014
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20140001462
    Abstract: A method of fabricating a stable, high mobility metal oxide thin film transistor includes the steps of providing a substrate, positioning a gate on the substrate, and depositing a gate dielectric layer on the gate and portions of the substrate not covered by the gate. A multiple film active layer including a metal oxide semiconductor film and a metal oxide passivation film is deposited on the gate dielectric with the passivation film positioned in overlying relationship to the semiconductor film. An etch-stop layer is positioned on a surface of the passivation film and defines a channel area in the active layer. A portion of the multiple film active layer on opposite sides of the etch-stop layer is modified to form an ohmic contact and metal source/drain contacts are positioned on the modified portion of the multiple film active layer.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong, Tian Xiao, Juergen Musolf
  • Patent number: 8592817
    Abstract: A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: November 26, 2013
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20130143395
    Abstract: A thin film semiconductor device has a semiconductor layer including a mixture of an amorphous semiconductor ionic metal oxide and an amorphous insulating covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a conductive channel, and a gate terminal is positioned in communication with the conductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.
    Type: Application
    Filed: February 4, 2013
    Publication date: June 6, 2013
    Inventors: Chan-Long Shieh, Gang Yu
  • Publication number: 20130119396
    Abstract: Two-terminal switching devices characterized by high on/off current ratios and by high breakdown voltage are provided. These devices can be employed as switches in the driving circuits of active matrix displays, e.g., in electrophoretic, rotating element and liquid crystal displays. The switching devices include two electrodes, and a layer of a broad band semiconducting material residing between the electrodes. According to one example, the cathode comprises a metal having a low work function, the anode comprises an organic material having a p+ or p++ type of conductivity, and the broad band semiconductor comprises a metal oxide. The work function difference between the cathode and the anode material is preferably at least about 0.6 eV. The on/off current ratios of at least 10,000 over a voltage range of about 15 V can be achieved. The devices can be formed, if desired, on flexible polymeric substrates having low melting points.
    Type: Application
    Filed: May 9, 2012
    Publication date: May 16, 2013
    Applicant: CBRITE INC.
    Inventors: Gang YU, Chan-Long SHIEH, Hsing-Chung LEE
  • Patent number: 8435832
    Abstract: A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: May 7, 2013
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 8377743
    Abstract: A method of annealing a metal oxide on a temperature sensitive substrate formation includes the steps of providing a temperature sensitive substrate formation and forming a spacer layer on a surface of the substrate formation. A metal oxide semiconductor device is formed on the spacer layer, the device includes at least a layer of amorphous metal oxide semiconductor material, an interface of the amorphous metal oxide layer with a dielectric layer, and a gate metal layer adjacent the layer of amorphous metal oxide semiconductor material and the interface. The method then includes the step of at least partially annealing the layer of metal oxide semiconductor material by heating the adjacent gate metal layer with pulses of infra red radiation to improve the mobility and operating stability of the amorphous metal oxide semiconductor material while retaining at least the amorphous metal oxide semiconductor material adjacent the gate metal layer amorphous.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: February 19, 2013
    Assignee: CBRITE Inc.
    Inventors: Chan-Long Shieh, Hsing-Chung Lee
  • Publication number: 20130032796
    Abstract: A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 7, 2013
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20120313092
    Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20120300147
    Abstract: A method of fabricating metal oxide TFTs on transparent substrates includes the steps of positioning an opaque gate metal area on the front surface of the substrate, depositing transparent gate dielectric and transparent metal oxide semiconductor layers overlying the gate metal and a surrounding area, depositing transparent passivation material on the semiconductor material, depositing photoresist on the passivation material, exposing and developing the photoresist to remove exposed portions, etching the passivation material to leave a passivation area defining a channel area, depositing transparent conductive material over the passivation area, depositing photoresist over the conductive material, exposing and developing the photoresist to remove unexposed portions, and etching the conductive material to leave source and drain areas on opposed sides of the channel area.
    Type: Application
    Filed: February 6, 2012
    Publication date: November 29, 2012
    Inventors: Chan-Long Shieh, Gang Yu
  • Publication number: 20120302003
    Abstract: A method of fabricating MOTFTs on transparent substrates includes positioning opaque gate metal on the front surface of a transparent substrate and depositing transparent gate dielectric, transparent metal oxide semiconductor material, and passivation material on the gate metal and the surrounding area. Portions of the passivation material are exposed from the rear surface of the substrate. Exposed portions are removed to define a channel area overlying the gate area. A relatively thick conductive metal material is selectively deposited on the exposed areas of the semiconductor material to form thick metal source/drain contacts. The selective deposition includes either plating or printing and processing a metal paste.
    Type: Application
    Filed: February 28, 2012
    Publication date: November 29, 2012
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 8273600
    Abstract: A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: September 25, 2012
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong
  • Publication number: 20120235138
    Abstract: A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.
    Type: Application
    Filed: May 26, 2012
    Publication date: September 20, 2012
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong, Liu-Chung Lee
  • Publication number: 20120218241
    Abstract: A method of driving a display device includes providing an array of pixels including rows and columns of pixels, each pixel including a switching/driving transistor circuit and at least one light emitting device. Each row of pixels has a scan line and each column of pixels has a data line. The method further includes defining a frame period during which each pixel in the array of pixels is addressed and dividing the frame period into a write subframe, a display subframe, and a rest subframe. A scan pulse is supplied to each scan line, a data signal to each data line and the light emitting devices are disabled during the write subframe. The light emitting devices are enabled during the display subframe and the switching/driving transistor circuits are disabled. A rest pulse is supplied to all scan lines and the light emitting devices are disabled during the rest subframe.
    Type: Application
    Filed: February 24, 2011
    Publication date: August 30, 2012
    Inventors: Chan-Long Shieh, Gang Yu
  • Publication number: 20120182284
    Abstract: An active matrix incorporated in a color display device includes an array of pixels arranged in n rows and m columns, each pixel having x elements including at least a red, a green, and a blue element. A plurality of m data lines, a different one of the plurality of m data lines being coupled one each to each column of pixels and to each element in each pixel in the column of pixels. A plurality of xn scan lines is provided, the xn scan lines being divided into n groups of x scan lines each. A different group of three xn scan lines is coupled to each row of the n rows of pixels and each of the different x scan lines in each group is coupled to a different one of the x elements.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Inventors: Chan-Long Shieh, Gang Yu
  • Patent number: 8222077
    Abstract: Two-terminal switching devices of MIM type having at least one electrode formed by a liquid phase processing method are provided for use in active matrix backplane applications; more specifically, MIM devices with symmetric current-voltage characteristics are applied for LCD active matrix backplane applications, and MIM devices with asymmetric current-voltage characteristics are applied for active matrix backplane implementation for electrophoretic displays (EPD) and rotating element displays. In particular, the combination of the bottom metal, metal-oxide insulator and solution-processible top conducting layer enables high throughput, roll-to-roll process for flexible displays.
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: July 17, 2012
    Assignee: Cbrite Inc.
    Inventors: Xiong Gong, Kaixia Yang, Gang Yu, Boo Jorgen Larŝ Nilsson, Chan-Long Shieh, Hsing-Chung Lee, Fatt Foong
  • Publication number: 20120168744
    Abstract: A method of fabricating MO TFTs on transparent substrates by positioning opaque gate metal on the front surface of the substrate defining a gate area, depositing gate dielectric material on the front surface of the substrate, overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material on the gate dielectric material. Depositing etch stop material on the semiconductor material. Positioning photoresist on the etch stop material, the etch stop material and the photoresist being selectively removable, and the photoresist defining an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the rear surface of the substrate using the gate metal as a mask and removing exposed portions so as to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT.
    Type: Application
    Filed: August 2, 2011
    Publication date: July 5, 2012
    Inventors: Chan-Long Shieh, Gang Yu, Fatt Foong