Abstract: A power storage system includes n number of slave BMSs for transmitting data associated with an electric characteristic value of battery cells, included in battery modules managed by the slave BMSs, through slave communication networks; m number of master BMSs for primarily processing the data associated with an electric characteristic value of battery cells, transmitted through the slave communication networks, and transmitting the primarily processed data through a master communication network; and a super master BMS for secondarily processing the data transmitted through the master communication network. Since the data transmitted from each slave BMS are processed in a master BMSs, the amount of data loaded on a communication line may decrease. Therefore, even though the capacity of a power storage system increases, rapid data collection and data control may be achieved.

Abstract: Disclosed is a unit rack for power storage having a plurality of cell modules which are series- or parallel-connected with each other; a housing for accommodating the cell modules; a receiving part of a circuit breaker, formed or installed in the housing, and having a ground clearance higher than the highest ground clearance of the cell modules; a circuit breaker received in the receiving part and connected between the connection lines; and a receiving part cover for closing the receiving part of the circuit breaker.

Abstract: Provided are a method and apparatus for avoiding bank conflict. A first instruction that is one of access instructions that are predicted to cause the bank conflict is replaced with a second instruction by changing an execute timing of the first instruction to a timing prior to the execute timing of the first instruction so as for the access instructions not to cause the bank conflict. Next, a load/store unit that is scheduled to access the bank according to the first instruction accesses the bank and reads out a data from the bank at an execute timing of the second instruction, and after that, the load/store unit is allowed to be inputted the read data at the execute timing of the first instruction. Accordingly, although the access instructions that are predicted to cause the bank conflict are allocated to the load/store units, the bank conflict can be prevented, so that it is possible to avoid deterioration in performance due the occurrence of the bank conflict.

Abstract: An image rendering apparatus may include a buffer memory unit and a processor. The buffer memory unit may store input ray data for image rendering according to a ray tracing scheme while shape data corresponding to the input ray data is being fetched from a cache. The processor may output the received shape data together with the input ray data to an operation apparatus.

Abstract: A method and apparatus for processing a vertex may fetch pieces of position information of vertexes, may extract pieces of target position information from the fetched pieces of position information, may perform tile binning on the pieces of target position information, may fetch pieces of attribute information having same indexes as the pieces of target position information, and may shade the fetched pieces of attribute information.

Abstract: Provided is an image processing apparatus. The image processing apparatus may perform an intersection test for rendering of a ray tracing scheme. The image processing apparatus may include a first calculator and a second calculator. The first calculator may perform a ray-plane test to determine whether a ray intersects a plane including a primitive and a barycentric test to determine whether the ray intersects the primitive. The second calculator may calculate a hit point based on the ray which intersects the primitive.

Abstract: Disclosed are an apparatus and a method for back-face culling using coherence between chronologically adjacent frames. The apparatus and the method determine whether face properties of polygons are changed based on a matrix reflecting three-dimensional motion of a frame. When the face properties are not changed, face properties of the polygons used in a process of a previous frame are reused to cull back-face polygons.

Abstract: A method to discard pixels early includes a first early depth test maintaining a depth value on a pixel to be discarded by a discard instruction, and a second early depth test updating the depth value on a pixel not to be discarded by the discard instruction. Because of the first and second early depth tests, a number of pixels to be processed by a pixel shading process may be reduced.

Abstract: According to the present invention, a service is configured by a plurality of sessions and respective session negotiation requests defined by different media formats can be performed without influencing existing connected sessions, and hence it is easy to add, delete, and change the media, the contact of session negotiation can be specified, and the response to the session negotiation request can be processed easily with the service acceptance or rejection of the contact.

Abstract: An image processing apparatus is provided. A splitting unit of the image processing apparatus may split a first space within an input three-dimensional (3D) model into a plurality of subspaces in order to generate an acceleration structure of the input 3D model. A decision unit of the image processing apparatus may set a subspace determined as having a relatively high probability of including a ray progress path among the plurality of subspaces, as a child node having a relatively high traversal priority in the acceleration structure among a plurality of child nodes.

Abstract: Provided is a method and of controlling a voltage of power supplied to a 3-dimensional (3D) graphics data processor and the 3D graphics data processor using the method. The method includes controlling the voltage of the power supplied to the graphics data processor based on the amount of data representing an object included in graphics data and re-controlling the voltage of the power supplied to the graphics data processor based on a time difference between scheduled processing time according to the controlled voltage for the object and actual processing time consumed by the graphics data processor, thereby reducing power consumption.

Abstract: Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream processors based on stream processor status information, and input data into the selected stream processor. The stream processor status information may include first status information of a processor core and second status information of at least one internal memory.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.

Abstract: Provided is an image processing apparatus. Ray tracing may be performed using a general scheme with respect to a plurality of reference pixels among pixels of an image to be rendered. With respect to a pixel excluding the reference pixels, geometry information may be interpolated based on a ray tracing result of adjacent reference pixels.

Abstract: A photographing method, medium, and apparatus based on face detection in a portable camera. The portable photographing apparatus may include an image input unit that receives an image, a face detection unit that detects a face from the received image, a storage unit that stores the image detected by the face detection unit as a moving image in a first mode, and a quality evaluation unit that evaluates the quality of the image detected by the face detection unit and stores the same as a still image in a second mode upon satisfaction of predetermined conditions evaluated based on the quality evaluation of the still image.

Abstract: A photographing method, medium, and apparatus based on face detection in a portable camera. The portable photographing apparatus may include an image input unit that receives an image, a face detection unit that detects a face from the received image, a storage unit that stores the image detected by the face detection unit as a moving image in a first mode, and a quality evaluation unit that evaluates the quality of the image detected by the face detection unit and stores the same as a still image in a second mode upon satisfaction of predetermined conditions evaluated based on the quality evaluation of the still image.

Abstract: A selector of an image processing apparatus may select, from a plurality of sub-pixels included in a first pixel, at least one sub-pixel to be anti-aliased. A processor of the image processing apparatus may calculate a color value of the first pixel by performing an anti-aliasing process with respect to each of the selected at least one sub-pixel.

Abstract: A system and method of rendering three-dimensional (3D) graphics. The system for rendering 3D graphics may include a plurality of cores including a scratch pad memory, a first memory to perform a control flow, a second memory for loop acceleration, and a shared memory to interpolate with the plurality of cores.

Abstract: Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream processors based on stream processor status information, and input data into the selected stream processor. The stream processor status information may include first status information of a processor core and second status information of at least one internal memory.

Abstract: A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.