Patents by Inventor Chan Seob Cho

Chan Seob Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9368453
    Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung Yu Hsieh, Hui Peng Koh
  • Publication number: 20160079180
    Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Inventors: Guoxiang NING, Chan Seob CHO, Paul ACKMANN, Jung Yu HSIEH, Hui Peng KOH
  • Patent number: 9252061
    Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: February 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Guoxiang Ning, Chan Seob Cho, Paul Ackmann, Jung Yu Hsieh, Hui Peng Koh
  • Publication number: 20150287651
    Abstract: A method of forming dummy structures and an overlay mark protection zone over an active layer zone based on the shape of an overlay mark and the resulting device are provided. Embodiments include determining a size and a shape of an overlay mark; determining a size and a shape of an overlay mark protection zone based on the shape of the overlay mark; determining a shape of a plurality of dummy structures based on the shape of the overlay mark; determining a size and a shape of an active layer zone based on the size and the shape of the overlay mark and the plurality of dummy structures; forming the active layer zone in an active layer of a semiconductor substrate; forming the overlay mark and the plurality of dummy structures over the active layer zone in a poly layer of the semiconductor substrate; and planarizing the poly layer.
    Type: Application
    Filed: April 2, 2014
    Publication date: October 8, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Guoxiang NING, Chan Seob CHO, Paul ACKMANN, Jung Yu HSIEH, Hui Peng KOH
  • Patent number: 6602649
    Abstract: Photoresist monomers which can be used to form photoresist polymers and photoresist compositions using the same which are suitable for photolithography processes employing a deep ultraviolet light source and copolymers thereof. Monomers are represented by following Formula 1: wherein, R1, is —OH or —R—OH; R represents substituted or unsubstituted linear or branched (C1-C10) alkylene, substituted or unsubstituted (C1-C10) alkylene comprising an ether linkage, substituted or unsubstituted (C1-C10) alkylene comprising an ester linkage, or substituted or unsubstituted (C1-C10) alkylene comprising an ketone moiety; and 1 is an integer of 1 or 2.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: August 5, 2003
    Assignee: Hynix Semiconductor Inc
    Inventors: Chi Hyeong Roh, Seung Hyuk Lee, Chan Seob Cho
  • Publication number: 20020015912
    Abstract: Photoresist monomers which can be used to form photoresist polymers and photoresist compositions using the same which are suitable for photolithography processes employing a deep ultraviolet light source and copolymers thereof.
    Type: Application
    Filed: June 15, 2001
    Publication date: February 7, 2002
    Inventors: Chi Hyeong Roh, Seung Hyuk Lee, Chan Seob Cho
  • Patent number: 5675402
    Abstract: The present invention discloses a light control means in a stepper.The light control means of the present invention has a twofold structure consisted of at least more than two blades which open a circuit pattern designed on a reticle; and a subblade which can close selectively a portion of the circuit pattern. The sub-blade is mounted above or below one of the at least more than two blades, and is movable in every directions in response to the instruction from the blade control system.Accordingly, the present invention provides a exposure process which can selectively cover only the dies that will be overlapped with the EBR gap of the wafer using sub-blade, thereby increasing the number of the net-die.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: October 7, 1997
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Chan Seob Cho, Hwan Soo Chang, Myung Gun Gil