Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A circuit modeling system includes a store a first net list. The first net list includes a plurality of semiconductor devices, a first power distribution network (PDN) connected to the plurality of semiconductor devices, and a signal network connected to the plurality of semiconductor devices that transmits signals to the plurality of semiconductor devices. A circuit simulation unit is configured to identify first semiconductor devices and second semiconductor devices from among the plurality of semiconductor devices. The first semiconductor devices are activated by receiving a signal through the signal network, and the second semiconductor devices are inactive. The circuit simulation unit is configured to reduce the first PDN to a second PDN based on the identified first semiconductor devices, and to generate a second net list including the signal network, the second PDN, and the first semiconductor devices.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.

Abstract: A method of analyzing power noise in a semiconductor device includes; generating modified current information by modifying present current information based on a previous analysis result, updating a current vector based on the modified current information, and generating a present analysis result by calculating a voltage vector from the updated current vector.

Abstract: A circuit modeling system includes a store a first net list. The first net list includes a plurality of semiconductor devices, a first power distribution network (PDN) connected to the plurality of semiconductor devices, and a signal network connected to the plurality of semiconductor devices that transmits signals to the plurality of semiconductor devices. A circuit simulation unit is configured to identify first semiconductor devices and second semiconductor devices from among the plurality of semiconductor devices. The first semiconductor devices are activated by receiving a signal through the signal network, and the second semiconductor devices are inactive. The circuit simulation unit is configured to reduce the first PDN to a second PDN based on the identified first semiconductor devices, and to generate a second net list including the signal network, the second PDN, and the first semiconductor devices.

Abstract: A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters.

Abstract: An integrated circuit (IC) is designed by generating a circuit diagram of the IC using one or more blocks. An information repository is provided that contains layout information that is associated with one or more template blocks. A symbol layout abstraction model is then generated by associating the layout information that is associated with one or more of the template blocks with at least one of the circuit diagram blocks of the IC.

Abstract: An integrated circuit (IC) is designed by generating a circuit diagram of the IC using one or more blocks. An information repository is provided that contains layout information that is associated with one or more template blocks. A symbol layout abstraction model is then generated by associating the layout information that is associated with one or more of the template blocks with at least one of the circuit diagram blocks of the IC.