Patents by Inventor Chan Seung Hwang

Chan Seung Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9070701
    Abstract: A semiconductor device is provided. The semiconductor device includes first and second storage electrodes formed to be spaced apart from each other on a substrate, an insulating continuous support pattern connected to top surfaces of the first and second storage electrodes, a storage dielectric layer formed to cover the first and second storage electrodes and the continuous support pattern, and a plate electrode formed on the storage dielectric layer. The continuous support pattern includes a first contact part connected to the top surface of the first storage electrode, a second contact part connected to the top surface of the second storage electrode, and a connection part connecting the first and second contact parts with each other.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Hee Lim, Chan-Seung Hwang
  • Patent number: 6621164
    Abstract: A semiconductor device including a semiconductor integrated circuit chip having a semiconductor substrate, a plurality of chip pads positioned on a surface of the substrate, a passivation layer formed on the substrate and having openings to expose the chip pads. A first polymer layer is formed on the passivation layer, a patterned first under barrier metal (UBM) layer formed on the chip pads and the first polymer layer, a plurality of redistribution pattern formed on the first UBM, with each redistribution pattern having a concave pattern in a bump pad area. A second polymer layer is formed on the first polymer layer and the redistribution pattern, the second polymer layer having openings for exposing the bump pad areas, a second under barrier metal (UBM) formed on the bump pads. A plurality of solder bumps is formed on the second UBM and electrically connected to the redistribution pattern in the bump pad area.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: September 16, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Seung Hwang, Seung Ouk Jung
  • Publication number: 20020185721
    Abstract: A semiconductor device including a semiconductor integrated circuit chip having a semiconductor substrate, a plurality of chip pads positioned on a surface of the substrate, a passivation layer formed on the substrate and having openings to expose the chip pads. A first polymer layer is formed on the passivation layer, a patterned first under barrier metal (UBM) layer formed on the chip pads and the first polymer layer, a plurality of redistribution pattern formed on the first UBM, with each redistribution pattern having a concave pattern in a bump pad area. A second polymer layer is formed on the first polymer layer and the redistribution pattern, the second polymer layer having openings for exposing the bump pad areas, a second under barrier metal (UBM) formed on the bump pads. A plurality of solder bumps is formed on the second UBM and electrically connected to the redistribution pattern in the bump pad area.
    Type: Application
    Filed: July 30, 2002
    Publication date: December 12, 2002
    Inventors: Chan Seung Hwang, Seung Ouk Jung
  • Patent number: 6492198
    Abstract: A semiconductor device includes a semiconductor chip, a first polymer layer on passivation of the semiconductor chip, patterned first under barrier metal (UBM) layers on the first polymer layer and chip pads exposed by the first polymer layer and the passivation, a copper redistribution pattern on the first UBM layers, said copper redistribution pattern electrically connected to the chip pads, a barrier metal on the copper redistribution pattern, a second polymer layer on the first polymer layer and the copper redistribution pattern, and external connecting electrodes on portions of the copper redistribution pattern exposed by the second polymer layer. The barrier metal is chrome (Cr), nickel (Ni), or nickel-chrome (Ni—Cr) in one or more layers. The barrier metal may further include a metal inner complex formed by reacting the surface the Cr or Ni layer with a silane or an azole group solution.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: December 10, 2002
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Chan Seung Hwang
  • Patent number: 6455408
    Abstract: A semiconductor device including a semiconductor integrated circuit chip having a semiconductor substrate, a plurality of chip pads positioned on a surface of the substrate, a passivation layer formed on the substrate and having openings to expose the chip pads. A first polymer layer is formed on the passivation layer, a patterned first under barrier metal (UBM) layer formed on the chip pads and the first polymer layer, a plurality of redistribution pattern formed on the first UBM, with each redistribution pattern having a concave pattern in a bump pad area. A second polymer layer is formed on the first polymer layer and the redistribution pattern, the second polymer layer having openings for exposing the bump pad areas, a second under barrier metal (UBM) formed on the bump pads. A plurality of solder bumps is formed on the second UBM and electrically connected to the redistribution pattern in the bump pad area.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: September 24, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chan Seung Hwang, Seung Ouk Jung
  • Publication number: 20020020855
    Abstract: A semiconductor device includes a semiconductor chip, a first polymer layer on passivation of the semiconductor chip, patterned first under barrier metal (UBM) layers on the first polymer layer and chip pads exposed by the first polymer layer and the passivation, a copper redistribution pattern on the first UBM layers, said copper redistribution pattern electrically connected to the chip pads, a barrier metal on the copper redistribution pattern, a second polymer layer on the first polymer layer and the copper redistribution pattern, and external connecting electrodes on portions of the copper redistribution pattern exposed by the second polymer layer. The barrier metal is chrome (Cr), nickel (Ni), or nickel-chrome (Ni—Cr) in one or more layers. The barrier metal may further include a metal inner complex formed by reacting the surface the Cr or Ni layer with a silane or an azole group solution.
    Type: Application
    Filed: September 26, 2001
    Publication date: February 21, 2002
    Inventor: Chan Seung Hwang
  • Patent number: 5923957
    Abstract: A lead-on-chip semiconductor device package is formed by attaching a lead frame to the chip with a discontinuous adhesive layer. Electrode pads of the chip are electrically connected by bonding wires and mechanically connected by the adhesive layer to the lead frame, and then encapsulated by an encapsulant such as molding compound. The adhesive layer is formed from a liquid adhesive material having a certain viscosity. Although the liquid adhesive is continuously applied to top surfaces of the inner leads as well as gaps between adjacent inner leads, the adhesive layer is formed only on the top surfaces of the inner leads while the liquid adhesive falls through the gaps. Thermoplastic or thermosetting resins may be used as the liquid adhesive.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: July 13, 1999
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jae Song, Jeong Woo Seo, Seung Ho Ann, Chan Seung Hwang