Patents by Inventor Chandramani

Chandramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934695
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chandramani, Dinesh Agarwal, Sharath Shivakumar, Ruchir Sinha
  • Publication number: 20220413756
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may convert unaligned write commands into aligned write commands and generate unaligned information associated with the unaligned write commands. In some aspects, the unaligned information indicates offset information for each unaligned write command. The controller may accumulate a threshold size of aligned write command transfer sizes in an aggregation command queue and fetch pre-pad or post-pad data for each unaligned write command in parallel based on the aggregation command queue having accumulated the threshold size of aligned write command transfer sizes. The controller may transfer host data for each unaligned write command to a data buffer at a corresponding offset within the data buffer based on the unaligned information. The controller may generate aligned data using the pre-pad or post-pad data combined with the host data and program the aligned data into a memory die.
    Type: Application
    Filed: June 23, 2021
    Publication date: December 29, 2022
    Inventors: CHANDRAMANI ., Dinesh AGARWAL, Sharath SHIVAKUMAR, Ruchir SINHA
  • Patent number: 11456050
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 27, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Chandramani, Sagar Shirpimutt
  • Publication number: 20220270703
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow sub-blocks with different sub-block addresses to be linked across multiple planes to form metablocks. The memory includes multiple blocks in different planes, where each of the blocks includes multiple sub-blocks. The controller links a first sub-block in a first plane and a second sub-block in a second plane with different sub-block addresses to form the metablock. After forming the metablock, the controller programs different word lines in the first and second sub-blocks when writing data to the metablock. Thus, the controller may write data to linked or relinked metablocks with different sub-block addresses, thereby improving die yield and memory capacity of the storage device.
    Type: Application
    Filed: February 24, 2021
    Publication date: August 25, 2022
    Inventors: Chandramani, Sagar Shirpimutt
  • Publication number: 20220229789
    Abstract: A Host Memory Buffer (HMB) Abstraction Protocol layer is individually included in a host device and a SD-PCIe device. The HMB Abstraction Protocol layers provide the SD-PCIe device access to a HMB region of the host device when the SD-PCIe is operating in the SD mode, where the HMB region was previously inaccessible to the SD-PCIe device when operating in the SD mode.
    Type: Application
    Filed: February 22, 2021
    Publication date: July 21, 2022
    Inventors: Rakesh Balakrishnan, Yuvaraj Kumar, Chandramani
  • Publication number: 20220155480
    Abstract: A method for modeling a subterranean formation includes measuring or receiving cross-well electromagnetic data representing a subterranean formation. The method also includes producing a resistivity profile of the subterranean formation based at least partially upon the cross-well electromagnetic data. The method also includes determining a static model of the subterranean formation based at least partially upon the resistivity profile. The method also includes determining a dynamic model of the subterranean formation based at least partially upon the static model.
    Type: Application
    Filed: March 24, 2020
    Publication date: May 19, 2022
    Inventors: Shubham Mishra, Aditya Ojha, Chandramani Shrivastava
  • Publication number: 20210331975
    Abstract: The present invention provides particular a novel composition for manufacturing plastic composites and a process thereof. Said invention provides a composition and a process utilizes any or all kind of plastic waste in manufacturing composites and thereby is economical and environment friendly. It utilizes any or all kind of plastic wastes includes road waste, soft & hard form of plastic waste. Moreover, it eliminates the use of cement and utilizes plastic wastes in manufacturing composites; therefore is environment friendly. Said present compositions utilizes plastic waste in manufacturing light weight composites that are highly stable with increased strength, shelf life and durability. Said composition is fire resistant with increased strength withstanding heavy load.
    Type: Application
    Filed: October 7, 2019
    Publication date: October 28, 2021
    Applicant: SALTECH DESIGN LABS PRIVATE LIMITED
    Inventors: Aditya Suraj SHUKLA, Sudhirkumar Chandramani SHUKLA, Yogesh kumar Rameshvar SHARMA