Patents by Inventor Chandramouleeswaran Subramani

Chandramouleeswaran Subramani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11908820
    Abstract: An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventor: Chandramouleeswaran Subramani
  • Publication number: 20220165697
    Abstract: An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.
    Type: Application
    Filed: February 9, 2022
    Publication date: May 26, 2022
    Applicant: Intel Corporation
    Inventor: Chandramouleeswaran Subramani
  • Patent number: 11322469
    Abstract: An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventor: Chandramouleeswaran Subramani
  • Patent number: 11319334
    Abstract: An integrated circuit (IC) package comprising a substrate having a dielectric, a first structure over at least a portion of the dielectric, the first structure comprising a molecular compound having a ligand coordinating moiety and a second structure over at least a portion of the first structure, the second structure comprising a metal, wherein the first structure is chemically bonded to the dielectric.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventor: Chandramouleeswaran Subramani
  • Publication number: 20190202845
    Abstract: An integrated circuit (IC) package comprising a substrate having a dielectric, a first structure over at least a portion of the dielectric, the first structure comprising a molecular compound having a ligand coordinating moiety and a second structure over at least a portion of the first structure, the second structure comprising a metal, wherein the first structure is chemically bonded to the dielectric.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: INTEL CORPORATION
    Inventor: Chandramouleeswaran Subramani
  • Publication number: 20190189581
    Abstract: An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Applicant: Intel Corporation
    Inventor: Chandramouleeswaran Subramani
  • Patent number: 10073340
    Abstract: Various embodiments disclosed relate to protein films and methods of making the same. In various embodiments, the present invention provides a method of making a protein film including placing on a substrate a protein solution, to form a precursor protein film. The protein solution includes one or more proteins. The method includes compressing the precursor protein film to form a protein film.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 11, 2018
    Assignee: University of Massachusetts
    Inventors: Vincent M Rotello, Bradley Duncan, Li-Sheng Wang, Eunhee Jeoung, Chandramouleeswaran Subramani, Krishnendu Saha
  • Publication number: 20160096935
    Abstract: Various embodiments disclosed relate to protein films and methods of making the same. In various embodiments, the present invention provides a method of making a protein film including placing on a substrate a protein solution, to form a precursor protein film. The protein solution includes one or more proteins. The method includes compressing the precursor protein film to form a protein film.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 7, 2016
    Inventors: Vincent M. Rotello, Bradley Duncan, Li-Sheng Wang, Eunhee Jeoung, Chandramouleeswaran Subramani, Krishnendu Saha
  • Patent number: 9147603
    Abstract: A microelectronic structure may include an interconnect structure, an amine functional reactive polymer layer grafted onto the interconnect structure, and a dielectric layer on the amine functional reactive polymer layer, wherein the dielectric layer is bonded to the polymer layer with an amine bond. In one embodiment, the interconnect structure may be fabricated from a copper containing material. In a further embodiment, the dielectric layer may comprise an oxygen functional reactive dielectric layer, such as an epoxy dielectric layer. In one method of fabricating the microelectronic structure, the amine functional reactive polymer layer may be grafted onto the interconnect structure by an initiated chemical vapor deposition process.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: September 29, 2015
    Assignee: Intel Corporation
    Inventors: Chandramouleeswaran Subramani, Ravindra V. Tanikella
  • Publication number: 20150206793
    Abstract: A microelectronic structure may include an interconnect structure, an amine functional reactive polymer layer grafted onto the interconnect structure, and a dielectric layer on the amine functional reactive polymer layer, wherein the dielectric layer is bonded to the polymer layer with an amine bond. In one embodiment, the interconnect structure may be fabricated from a copper containing material. In a further embodiment, the dielectric layer may comprise an oxygen functional reactive dielectric layer, such as an epoxy dielectric layer. In one method of fabricating the microelectronic structure, the amine functional reactive polymer layer may be grafted onto the interconnect structure by an initiated chemical vapor deposition process.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 23, 2015
    Inventors: Chandramouleeswaran Subramani, Ravindra V. Tanikella