Abstract: An example method comprises receiving historical wind turbine failure data and asset data from SCADA systems, receiving first historical sensor data, determining healthy assets of the renewable energy assets by comparing signals to known healthy operating signals, training at least one machine learning model to indicate assets that may potentially fail and to a second set of assets that are operating within a healthy threshold, receiving first current sensor data of a second time period, applying a machine learning model to the current sensor data to generate a first failure prediction a failure and generate a list of assets that are operating within a healthy threshold, comparing the first failure prediction to a trigger criteria, generating and transmitting a first alert if comparing the first failure prediction to the trigger criteria indicates a failure prediction, and updating a list of assets to perform surveillance if within a healthy threshold.

Abstract: An example method comprises receiving historical wind turbine failure data and asset data from SCADA systems, receiving first historical sensor data, determining healthy assets of the renewable energy assets by comparing signals to known healthy operating signals, training at least one machine learning model to indicate assets that may potentially fail and to a second set of assets that are operating within a healthy threshold, receiving first current sensor data of a second time period, applying a machine learning model to the current sensor data to generate a first failure prediction a failure and generate a list of assets that are operating within a healthy threshold, comparing the first failure prediction to a trigger criteria, generating and transmitting a first alert if comparing the first failure prediction to the trigger criteria indicates a failure prediction, and updating a list of assets to perform surveillance if within a healthy threshold.

Abstract: An example method comprises receiving historical wind turbine failure data and asset data from SCADA systems, receiving first historical sensor data, determining healthy assets of the renewable energy assets by comparing signals to known healthy operating signals, training at least one machine learning model to indicate assets that may potentially fail and to a second set of assets that are operating within a healthy threshold, receiving first current sensor data of a second time period, applying a machine learning model to the current sensor data to generate a first failure prediction a failure and generate a list of assets that are operating within a healthy threshold, comparing the first failure prediction to a trigger criteria, generating and transmitting a first alert if comparing the first failure prediction to the trigger criteria indicates a failure prediction, and updating a list of assets to perform surveillance if within a healthy threshold.

Abstract: A method for assessing an asset status is provided. The method may include identifying, by a processor, an asset within a plurality of tangible, deployed assets. The method may also include retrieving a plurality of images from at least one data repository, whereby the plurality of images are captured within a preconfigured distance of the identified asset. The method may further include determining a portion of the retrieved plurality of images depict the identified asset. The method may also include performing a plurality of image processing techniques on the determined portion. The method may further include creating an assessment of the asset status of the identified asset based on the performed plurality of image processing techniques, whereby the created assessment details whether the identified asset needs a repair or a replacement.

Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

Abstract: A method for locating an anomaly in a fluid transmission pipeline system is provided. The method may include receiving data for one or more physical conditions measured at an input and output of a pipeline portion, performing multiple simulations on a model of the pipeline portion to determine sets of simulated conditions that respectively correspond to simulated leak locations, determining a probability for a leak at one or more of the simulated leak locations by comparing one or more sets of simulated conditions to the received output data, and determining a highest probability location for the leak based on the probability for the leak at the one or more of the simulated leak locations. At least one simulation of the multiple simulations may be performed as a stochastic process and may be based on the received input data.

Abstract: A method for locating an anomaly in a fluid transmission pipeline system is provided. The method may include receiving data for one or more physical conditions measured at an input and output of a pipeline portion, performing multiple simulations on a model of the pipeline portion to determine sets of simulated conditions that respectively correspond to simulated leak locations, determining a probability for a leak at one or more of the simulated leak locations by comparing one or more sets of simulated conditions to the received output data, and determining a highest probability location for the leak based on the probability for the leak at the one or more of the simulated leak locations. At least one simulation of the multiple simulations may be performed as a stochastic process and may be based on the received input data.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.

Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

Abstract: Systems and methods for improving timing closure of new and existing IC chips by breaking at least one parameter of interest into two or more partial parameters. More specifically, a method is provided for that includes propagating at least one timing analysis run for a semiconductor product. The method further includes identifying at least one parameter of interest used in the at least one timing analysis run. The method further includes splitting the at least one parameter into two parts comprising a controlled part and an uncontrolled part. The method further includes correlating or anti-correlating the controlled part with another parameter used in the at least one timing analysis run. The method further includes projecting timing using the correlation or anti-correlation between the controlled part and the another parameter and using the uncontrolled part of the at least one parameter.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Abstract: Statistically modeling timing in a digital circuit through the use of canonical form models, where some terms of the form represent sources of variation sensitive to only a subset of timing regions of the circuit. When propagating the form through regions through which some set of terms in the model is not sensitive, those terms are collapsed by placing them in a cache and replacing them in the form with a single combined term that references the cached terms.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In accordance with aspects of the present disclosure, a computer-implemented method for statistical static timing analysis of an integrated circuit is provided. The method may comprise identifying a timing parameter that contributes to a delay calculation. The method may further comprise determining, by a processing device, whether the identified timing parameter significantly impacts the delay calculation. The method may also comprise, responsive to determining that the identified timing parameter does not significantly impact the delay calculation, avoiding a sensitivity calculation for the identified timing parameter.

Abstract: Examples of techniques for statistical static timing analysis of an integrated circuit are disclosed. In one example according to aspects of the present disclosure, a computer-implemented method is provided. The method comprises performing an initial statistical static timing analysis of the integrated circuit to create a parameterized model of the integrated circuit for a plurality of paths using a plurality of timing corners to calculate a timing value for each of the plurality of paths, each of the plurality of timing corners representing a set of timing performance parameters. The method further comprises determining at least one worst timing corner from the parameterized model for each of the plurality of paths based on the initial statistical static timing analysis and calculated timing value for each of the plurality of paths. The method also comprises performing a subsequent analysis of the integrated circuit using the at least one worst timing corner.

Abstract: A system to improve performance of a semiconductor chip design includes a hierarchical analysis module that determines a hierarchical arrangement of the semiconductor chip design. The hierarchical arrangement includes a plurality of arcs located at different levels internal to the semiconductor chip design. The different levels include a macro level, a unit level and a core level. The system further includes a timing/load analysis module that determines first timing characteristics of at least one first arc in the macro level based on a first load applied to the at least one first arc. The system further determines second timing characteristics of at least one second arc in at least one of the unit level and the core level based on the first timing characteristics, with a portion of the second timing characteristics determined irrespective of the first load.

Abstract: Solutions for integrating manufacturing feedback into an integrated circuit design are disclosed. In one embodiment, a computer-implemented method is disclosed including: defining an acceptable yield requirement for a first integrated circuit product; obtaining manufacturing data about the first integrated circuit product; performing a regression analysis on data representing paths in the first integrated circuit product to define a plurality of parameter settings based upon the acceptable yield requirement and the manufacturing data; determining a projection corner associated with the parameter settings for satisfying the acceptable yield requirement; and modifying a design of a second integrated circuit product based upon the projection corner and the plurality of parameter settings.