Patents by Inventor Chandrasekaran Jagadeesan

Chandrasekaran Jagadeesan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10713109
    Abstract: Embodiments described herein provide a predictive failure analysis that enables design-time error and exception handling techniques to be supplemented or assisted by a predictive failure analysis system. One embodiment provides an electronic device, comprising a non-transitory machine-readable medium to store instructions; one or more processors to execute the instructions; and a memory coupled to the one or more processors, the memory to store the instructions which, when executed by the one or more processors, cause the one or more processors to receive injection of dynamic error detection logic into the instructions, the dynamic error handling logic including an error handling update to indicate a response to a predicted failure; receive a set of events indicative of the predicted failure; and respond to the set of events according to the error handling update.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: July 14, 2020
    Assignee: Apple Inc.
    Inventors: Anthony J. Tarlano, Nikhil A. Desai, Chandrasekaran Jagadeesan, Subash Sundaresan
  • Publication number: 20190102244
    Abstract: Embodiments described herein provide a predictive failure analysis that enables design-time error and exception handling techniques to be supplemented or assisted by a predictive failure analysis system. One embodiment provides an electronic device, comprising a non-transitory machine-readable medium to store instructions; one or more processors to execute the instructions; and a memory coupled to the one or more processors, the memory to store the instructions which, when executed by the one or more processors, cause the one or more processors to receive injection of dynamic error detection logic into the instructions, the dynamic error handling logic including an error handling update to indicate a response to a predicted failure; receive a set of events indicative of the predicted failure; and respond to the set of events according to the error handling update.
    Type: Application
    Filed: December 29, 2017
    Publication date: April 4, 2019
    Inventors: Anthony J. Tarlano, Nikhil A. Desai, Chandrasekaran Jagadeesan, Subash Sundaresan
  • Publication number: 20140019421
    Abstract: Systems, methods and computer-readable mediums are disclosed for a shared hardware and architecture for database systems. In some implementations, one or more source databases in a data warehouse can be backed up to one or more backup databases on network storage. During normal operating conditions, the backup databases are continuously updated with changes made to their corresponding source databases and metadata information for the database backup copies and database backup information are stored in a centralized repository of the system. When a source database fails (failover), the source database is replaced by its corresponding backup database on the network storage and the source database node (e.g., a server computer) is replaced by a standby node coupled to the network storage.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Applicant: APPLE INC.
    Inventor: Chandrasekaran Jagadeesan