Patents by Inventor Chandrashekar Krishnaswamy

Chandrashekar Krishnaswamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7623936
    Abstract: A method for determining priority of a selected workpiece in a process flow including a plurality of operations includes providing an objective function relating manufacturing losses to workpiece priority for the operations in the process flow. The objective function is solved to generate priority metrics for at least a subset of the operations remaining for the selected workpiece to allow completion of the selected workpiece in the process flow by a target completion due time.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: November 24, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peng Qu, Vijay Devarajan, Michael A. Hillis, Dax Middlebrooks, Farzad Sadjadi, Chandrashekar Krishnaswamy
  • Publication number: 20090157216
    Abstract: An automated, computer-implemented method for managing test wafers in an integrated, automated semiconductor manufacturing environment includes: managing a test wafer inventory; consuming inventoried test wafers in the automated process flow; and distributing the consumed test wafers according to their level of usage after an evaluation thereof. An automated, computer-implemented method for use in semiconductor manufacturing includes: monitoring test wafer utilization in an automated process flow; maintaining an inventory of test wafers of a plurality of different types responsive to the monitored utilization; and managing the test wafer utilization of the test wafer inventory.
    Type: Application
    Filed: December 14, 2007
    Publication date: June 18, 2009
    Inventors: CHANDRASHEKAR KRISHNASWAMY, Steven C. Nettles, Larry D. Barto
  • Patent number: 7460920
    Abstract: A method for processing workpieces in a process flow including a plurality of operations includes employing a fabrication simulation model of the process flow to determine an estimated completion time for a selected workpiece. The fabrication simulation model simulates the processing of the selected workpiece and other workpieces in the process flow through the plurality of operations. The priority of the selected workpiece is adjusted based on a comparison between a target completion time for the selected workpiece and the estimated completion time.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: December 2, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peng Qu, Vijay Devarajau, Michael A. Hillis, Dax Middlebrooks, Farzad Sadjadi, Chandrashekar Krishnaswamy
  • Patent number: 7444200
    Abstract: A method for scheduling preventative maintenance tasks includes defining a set of global time periods. Members of a set of preventative maintenance tasks associated with a plurality of machines for are scheduled execution during the global time periods based on capacities of the machines and production targets for the machines. A plurality of time slots is defined for a selected global period having a selected preventative maintenance task scheduled for execution therein. A selected time slot from the plurality of time slots is scheduled for performing the selected preventative maintenance task based on work in process levels for with the associated machine over the time slots.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: October 28, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peng Qu, Chandrashekar Krishnaswamy
  • Patent number: 7289867
    Abstract: The system includes a plurality of process modules and an independent module controller for each of the plurality of process modules that is adapted to control the process tools within each of the process modules. Each of the independent module controllers performs at least run-to-run control of the processing tools, yield management analysis, scheduling of materials provided to and sent from the process module, and movement of wafers within the process module. One method of the present invention involves providing a plurality of process modules, each of which has an independent module controller that is adapted to perform at least run-to-run control of the processing tools within the process module, yield management analysis, scheduling of materials, and movement of wafers within the process module. The independent module controller for each of the process modules controls the process tools within its respective process module that are employed in forming a portion of the integrated circuit device.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: October 30, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard J. Markle, Chandrashekar Krishnaswamy
  • Patent number: 7257502
    Abstract: A method for determining metrology sampling rates for workpieces in a process flow includes determining a current status of the process flow. Future processing of the workpieces in the process flow is simulated based on the current status of the process flow over a predetermined time horizon to predict sampling rates for the workpieces. During the simulating, sampling rules are implemented that consider capacity constraints of a metrology resource in the process flow. Actual workpieces in the process flow are sampled based on the predicted metrology sampling rates.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: August 14, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Peng Qu, Chandrashekar Krishnaswamy