Patents by Inventor Chandrashekar L. Chetput
Chandrashekar L. Chetput has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11334704Abstract: The present disclosure relates to a computer-implemented method for mixed signal design verification. Embodiments may include receiving, using a processor, an electronic circuit design and compiling and elaborating the electronic circuit design. Embodiments may also include simulating the electronic circuit design and updating, during the simulating, a System Verilog User-Defined Resolution function (“SV-UDR”) associated with the electronic circuit design.Type: GrantFiled: October 1, 2020Date of Patent: May 17, 2022Assignee: Cadence Design Systems, Inc.Inventors: Nan Zhang, Chandrashekar L. Chetput, Aaron Mitchell Spratt, Joseph Leo Zielke, Jr., Rajat Kanti Mitra
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Patent number: 9501592Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.Type: GrantFiled: March 15, 2013Date of Patent: November 22, 2016Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet S. Kolpekwar, Aaron M. Spratt, William S. Cranston, Chandrashekar L. Chetput
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Patent number: 8949753Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.Type: GrantFiled: March 15, 2013Date of Patent: February 3, 2015Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet S. Kolpekwar, Aaron M. Spratt, William S. Cranston, Chandrashekar L. Chetput
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Patent number: 8732630Abstract: Some embodiments provide support for real number modeling in SystemVerilog by defining built-in nettypes with real data type and resolution functions natively in SystemVerilog and allow a simple path for porting Verilog-AMS wreal modeling to SystemVerilog modeling. Some embodiments provide support for incompatible nettypes and for net coercion in SystemVerilog. Some embodiments provide support for SystemVerilog reals net connecting to electrical nets and support for SystemVerilog real signals connecting to Verilog-AMS wreal signals. Some embodiments combine the strengths of Verilog-AMS and SystemVerilog languages to build a solution for value conversion between incompatible nets and an effective way to configure, simulate, or verify mixed-signal designs that are written in SystemVerilog language.Type: GrantFiled: March 15, 2013Date of Patent: May 20, 2014Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet S. Kolpekwar, Aaron M. Spratt, William S. Cranston, Chandrashekar L. Chetput
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Patent number: 8661402Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.Type: GrantFiled: April 4, 2012Date of Patent: February 25, 2014Assignee: Cadence Design Systems, Inc.Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Patent number: 8640073Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: GrantFiled: May 20, 2013Date of Patent: January 28, 2014Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Iyengar Srinivasan
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Publication number: 20130326440Abstract: For increasing user control and insight into preparing a mixed semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignments of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: ApplicationFiled: May 20, 2013Publication date: December 5, 2013Applicant: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 8578322Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.Type: GrantFiled: April 4, 2012Date of Patent: November 5, 2013Assignee: Cadence Design Systems, Inc.Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Patent number: 8504346Abstract: Disclosed are methods, systems, and structures for implementing an improved approach for simulating mixed-signal electronic designs. An improved approach for providing seamless interaction between analog and digital blocks during simulation, even if the digital blocks include complex types or models.Type: GrantFiled: December 15, 2009Date of Patent: August 6, 2013Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet Kolpekwar, Chandrashekar L. Chetput
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Patent number: 8448116Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: GrantFiled: August 31, 2010Date of Patent: May 21, 2013Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 8296699Abstract: A system, method, and computer program product is disclosed for utilizing dual-value signals, such as hierarchical dual-value signals, for mixed-signal simulation. Such dual-value signals can hold both analog and digital representations of a signal and use the appropriate representations based on which block (analog or digital) for which there is an interaction.Type: GrantFiled: February 26, 2010Date of Patent: October 23, 2012Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar
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Patent number: 8255191Abstract: A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.Type: GrantFiled: April 30, 2009Date of Patent: August 28, 2012Assignee: Cadence Design Systems, Inc.Inventors: Abhijeet Kolpekwar, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Publication number: 20120198405Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.Type: ApplicationFiled: April 4, 2012Publication date: August 2, 2012Applicant: Cadence Design Systems, Inc.Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Publication number: 20120198411Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.Type: ApplicationFiled: April 4, 2012Publication date: August 2, 2012Applicant: Cadence Design Systems, Inc.Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Patent number: 8234617Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.Type: GrantFiled: October 1, 2009Date of Patent: July 31, 2012Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Donald J. O'Riordan
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Patent number: 8201137Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.Type: GrantFiled: March 6, 2009Date of Patent: June 12, 2012Assignee: Cadence Design Systems, Inc.Inventors: Pranav Bhushan, Chandrashekar L. Chetput, Timothy Martin O'Leary
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Patent number: 7979262Abstract: Connections between digital blocks and other circuit components, such as power supplies and clocks, are verified using a discrete property or object, such as a discrete discipline. A discrete discipline is defined for each value of an operating parameter, such as voltage or clock speed, that is used in a circuit design. Each discrete discipline is propagated throughout respective nets using bottom-up and/or top-down propagation. As a result, each digital net is associated with a power supply value through its corresponding discrete discipline. A determination is made whether two digital nets are connected to each other within the same digital island. If so, a determination is made whether the digital nets are compatible. If they have conflicting discrete disciplines, then they are not compatible and an error report or signal can be generated to identify the incompatibility and its location. Compatibility checks can disregard grounded digital nets.Type: GrantFiled: March 9, 2006Date of Patent: July 12, 2011Assignee: Cadence Design Systems, Inc.Inventors: Srinivasan Iyengar, Abhijeet Kolpekwar, Chandrashekar L. Chetput
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Publication number: 20110083114Abstract: A system, method, and computer program product is disclosed that recycle digital assertions for mixed-signal electronic designs. The approach enables the re-use of pure digital assertions which reference signals that turn out to resolve to analog due to the particular circuit configuration chosen during the verification process.Type: ApplicationFiled: October 1, 2009Publication date: April 7, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Chandrashekar L. CHETPUT, Abhijeet KOLPEKWAR, Donald J. O'RIORDAN
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Publication number: 20100333050Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: ApplicationFiled: August 31, 2010Publication date: December 30, 2010Applicant: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar
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Patent number: 7797659Abstract: For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog and digital portions. In some aspects, the methods provide block-based assignment of disciplines, as well as design partitioning. In other aspects, the methods provide for resolving a discipline to apply in a block from among multiple possible disciplines. In some aspects, error flagging may be available for detecting disciplines different from what provided for assignment in a block. Assignments may be indicated based on instance, cell, terminal, or library names and may be specified with wild cards. In still other aspects, the methods may be embodied by instructions on computer readable media, and in systems comprising general and special purpose computer hardware that may communicate with various storage facilities and over various networks.Type: GrantFiled: January 29, 2007Date of Patent: September 14, 2010Assignee: Cadence Design Systems, Inc.Inventors: Chandrashekar L. Chetput, Abhijeet Kolpekwar, Srinivasan Iyengar