Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage.

Abstract: In an example, an apparatus includes an analog switch having an n-type metal oxide semiconductor (NMOS) circuit in parallel with a p-type metal oxide semiconductor (PMOS) circuit between a switch input and a switch output. The analog switch is responsive to an enable signal that determines switch state thereof. The NMOS circuit includes a switch N-channel transistor coupled to a buffer N-channel transistor, a gate of the switch N-channel transistor coupled to the enable signal and a gate of the buffer N-channel transistor coupled to a modulated N-channel gate voltage. The PMOS circuit including a switch P-channel transistor coupled to a buffer P-channel transistor, a gate of the switch P-channel transistor coupled to a complement of the enable signal and a gate of the buffer P-channel transistor coupled to a modulated P-channel gate voltage.

Abstract: A Schmitt trigger inverter circuit can include a first inverter. The first inverter can include a first pull-up device, a first pull-down device and a second pull-down device. The first inverter can receive an input signal. The Schmitt trigger inverter circuit can include a second inverter coupled in series with the first inverter and including an output that generates an output signal. The Schmitt trigger inverter circuit further can include a switch coupled to the output of the second inverter circuit and that is selectively enabled by the output signal. The switch can couple a predetermined reference voltage to a source terminal of the first pull-down device when in an enabled state. Coupling the predetermined reference voltage to the source terminal of the first pull-down device can alter a threshold voltage of the Schmitt trigger inverter circuit.

Abstract: Methods and apparatus for receiving high voltage signals using a receiver designed in a low supply voltage technology are disclosed. One embodiment of an integrated circuit includes a single ended driver including an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor. An input pass gate is coupled to the single ended driver, and is configured as a PMOS pass gate coupled in parallel with the NMOS transistor in the single ended driver. In a low voltage mode, the NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to the receiver. In a high voltage mode, the PMOS pass gate is disabled, and the NMOS transistor and PMOS transistor form a second pass gate for transmitting the input signal to the receiver.