Patents by Inventor Chang Bum Yong
Chang Bum Yong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087958Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Peng SUO, Ying W. WANG, Guan Huei SEE, Chang Bum YONG, Arvind SUNDARRAJAN
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Patent number: 11854886Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: GrantFiled: June 23, 2022Date of Patent: December 26, 2023Assignee: Applied Materials, Inc.Inventors: Peng Suo, Ying W. Wang, Guan Huei See, Chang Bum Yong, Arvind Sundarrajan
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Publication number: 20220375886Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Applicant: STATS ChipPAC Pte. Ltd.Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
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Publication number: 20220328354Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: ApplicationFiled: June 23, 2022Publication date: October 13, 2022Inventors: Peng SUO, Ying W. WANG, Guan Huei SEE, Chang Bum YONG, Arvind SUNDARRAJAN
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Patent number: 11469191Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.Type: GrantFiled: March 21, 2020Date of Patent: October 11, 2022Assignee: STATS ChipPAC Pte. Ltd.Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
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Patent number: 11404318Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: GrantFiled: November 20, 2020Date of Patent: August 2, 2022Assignee: Applied Materials, Inc.Inventors: Peng Suo, Ying W. Wang, Guan Huei See, Chang Bum Yong, Arvind Sundarrajan
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Publication number: 20220165621Abstract: The present disclosure relates to through-via structures with dielectric shielding of interconnections for advanced wafer level semiconductor packaging. The methods described herein enable the formation of high thickness dielectric shielding layers within low aspect ratio through-via structures, thus facilitating thin and small-form-factor package structures having high I/O density with improved bandwidth and power.Type: ApplicationFiled: November 20, 2020Publication date: May 26, 2022Inventors: Peng SUO, Ying W. WANG, Guan Huei SEE, Chang Bum YONG, Arvind SUNDARRAJAN
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Publication number: 20200219832Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.Type: ApplicationFiled: March 21, 2020Publication date: July 9, 2020Applicant: STATS ChipPAC Pte. Ltd.Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
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Patent number: 10636753Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.Type: GrantFiled: November 8, 2018Date of Patent: April 28, 2020Assignee: STATS ChipPAC Pte. Ltd.Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
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Publication number: 20190088603Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.Type: ApplicationFiled: November 8, 2018Publication date: March 21, 2019Applicant: STATS ChipPAC Pte. Ltd.Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
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Patent number: 9837336Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.Type: GrantFiled: April 21, 2014Date of Patent: December 5, 2017Assignee: STATS ChipPAC, Pte. Ltd.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku
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Patent number: 9728415Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.Type: GrantFiled: December 19, 2013Date of Patent: August 8, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: Vinoth Kanna Chockanathan, Xing Zhao, Duk Ju Na, Chang Bum Yong
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Patent number: 9281274Abstract: An integrated circuit substrate via system, and method of manufacture therefor, includes: a substrate having a substrate via in the substrate; a buffer layer patterned over the substrate via, the buffer layer having a planar surface; and a substrate via cap patterned over the buffer layer, the substrate via cap having a planar surface based on the planar surface of the buffer layer.Type: GrantFiled: September 27, 2013Date of Patent: March 8, 2016Assignee: STATS ChipPAC Ltd.Inventors: Xing Zhao, Chang Bum Yong, Duk Ju Na, Kyaw Oo Aung, Ling Ji
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Publication number: 20150179544Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.Type: ApplicationFiled: December 19, 2013Publication date: June 25, 2015Applicant: STATS CHIPPAC, LTD.Inventors: Vinoth Kanna Chockanathan, Xing Zhao, Duk Ju Na, Chang Bum Yong
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Patent number: 8809191Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.Type: GrantFiled: December 13, 2011Date of Patent: August 19, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku
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Publication number: 20140225279Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: STATS ChipPAC, Ltd.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku
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Patent number: 8742591Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.Type: GrantFiled: December 21, 2011Date of Patent: June 3, 2014Assignee: STATS ChipPAC, Ltd.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku
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Publication number: 20130161824Abstract: A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: STATS CHIPPAC, LTD.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku
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Publication number: 20130147036Abstract: A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.Type: ApplicationFiled: December 13, 2011Publication date: June 13, 2013Applicant: STATS ChipPAC, Ltd.Inventors: Won Kyoung Choi, Chang Bum Yong, Jae Hun Ku